1. 16 Nov, 2005 6 commits
    • Guido Guenther's avatar
      [PATCH] PowerBook 6,1: headphone not detected after suspend · c0ce5c52
      Guido Guenther authored
      ever since suspend to disk works I had the problem that headphone
      (un)plugging doesn't get detected properly anymore after the first
      resume.
      Reloading the module worked around this ever since, however the real
      cause of the problem was that after a resume the driver only got
      interrupts on "unplug" not on "plug". Reactivating the headphone status
      interrupt in tumbler_resume fixes this. This shouldn't cause
      any trouble with software suspend, but it would be nice if somebody
      could confirm this:
      Signed-off-by: default avatarGuido Guenther <agx@sigxcpu.org>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      c0ce5c52
    • Benjamin Herrenschmidt's avatar
      [PATCH] powerpc: pci_64 fixes & cleanups · b5166cc2
      Benjamin Herrenschmidt authored
      I discovered that in some cases (PowerMac for example) we wouldn't
      properly map the PCI IO space on recent kernels. In addition, the code
      for initializing PCI host bridges was scattered all over the place with
      some duplication between platforms.
      
      This patch fixes the problem and does a small cleanup by creating a
      pcibios_alloc_controller() in pci_64.c that is similar to the one in
      pci_32.c (just takes an additional device node argument) that takes care
      of all the grunt allocation and initialisation work. It should work for
      both boot time and dynamically allocated PHBs.
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      b5166cc2
    • Michael Ellerman's avatar
      [PATCH] powerpc: More debugging fixups · f9e4ec57
      Michael Ellerman authored
      Add a few more missing includes of udbg.h
      Signed-off-by: default avatarMichael Ellerman <michael@ellerman.id.au>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      f9e4ec57
    • Michael Ellerman's avatar
      [PATCH] powerpc: Fixup debugging in lmb.c · eb481899
      Michael Ellerman authored
      Somewhere we lost the include of udbg.h in lmb.c. While we're there, add a DBG
      macro like every other file has and use it in lmb_dump_all().
      Signed-off-by: default avatarMichael Ellerman <michael@ellerman.id.au>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      eb481899
    • Benjamin Herrenschmidt's avatar
      [PATCH] powerpc: update defconfigs · 5444a5e9
      Benjamin Herrenschmidt authored
      My patch moving ppc64 RTC to genrtc was supposed to update all
      defconfigs, but for some reason, the patch actually posted only had the
      pseries one... ouch. This patch properly updates all defconfigs.
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      5444a5e9
    • Marcelo Tosatti's avatar
      [PATCH] ppc32 8xx: update_mmu_cache() needs unconditional tlbie · eb07d964
      Marcelo Tosatti authored
      Currently 8xx fails to boot due to endless pagefaults.
      
      Seems the bug is exposed by the change which avoids flushing the
      TLB when not necessary (in case the pte has not changed), introduced
      recently:
      
      __handle_mm_fault():
      
              entry = pte_mkyoung(entry);
              if (!pte_same(old_entry, entry)) {
                      ptep_set_access_flags(vma, address, pte, entry, write_access);
                      update_mmu_cache(vma, address, entry);
                      lazy_mmu_prot_update(entry);
              } else {
                      /*
                       * This is needed only for protection faults but the arch code
                       * is not yet telling us if this is a protection fault or not.
                       * This still avoids useless tlb flushes for .text page faults
                       * with threads.
                       */
                      if (write_access)
                              flush_tlb_page(vma, address);
              }
      
      The "update_mmu_cache()" call was unconditional before, which caused the TLB
      to be flushed by:
      
              if (pfn_valid(pfn)) {
                      struct page *page = pfn_to_page(pfn);
                      if (!PageReserved(page)
                          && !test_bit(PG_arch_1, &page->flags)) {
                              if (vma->vm_mm == current->active_mm) {
      #ifdef CONFIG_8xx
                              /* On 8xx, cache control instructions (particularly 
                               * "dcbst" from flush_dcache_icache) fault as write 
                               * operation if there is an unpopulated TLB entry 
                               * for the address in question. To workaround that, 
                               * we invalidate the TLB here, thus avoiding dcbst 
                               * misbehaviour.
                               */
                                      _tlbie(address);
      #endif
                                      __flush_dcache_icache((void *) address);
                              } else
                                      flush_dcache_icache_page(page);
                              set_bit(PG_arch_1, &page->flags);
                      }
      
      Which worked to due to pure luck: PG_arch_1 was always unset before, but
      now it isnt.
      
      The root of the problem are the changes against the 8xx TLB handlers introduced
      during v2.6. What happens is the TLBMiss handlers load the zeroed pte into
      the TLB, causing the TLBError handler to be invoked (thats two TLB faults per 
      pagefault), which then jumps to the generic MM code to setup the pte.
      
      The bug is that the zeroed TLB is not invalidated (the same reason
      for the "dcbst" misbehaviour), resulting in infinite TLBError faults.
      
      The "two exception" approach requires a TLB flush (to nuke the zeroed TLB)
      at each PTE update for correct behaviour:
      Signed-off-by: default avatarMarcelo Tosatti <marcelo.tosatti@cyclades.com>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      eb07d964
  2. 15 Nov, 2005 34 commits