- 07 Dec, 2023 17 commits
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Krzysztof Kozlowski authored
Soundwire Devicetree bindings expect the Soundwire controller device node to be named just "soundwire": sm8250-xiaomi-elish-boe.dtb: soundwire-controller@3250000: $nodename:0: 'soundwire-controller@3250000' does not match '^soundwire(@.*)?$' Reported-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
Bjorn Andersson <andersson@kernel.org>
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Krzysztof Kozlowski authored
Soundwire Devicetree bindings expect the Soundwire controller device node to be named just "soundwire": sc8280xp-lenovo-thinkpad-x13s.dtb: soundwire-controller@3210000: $nodename:0: 'soundwire-controller@3210000' does not match '^soundwire(@.*)?$' Reported-by:
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Krzysztof Kozlowski authored
There is no "multi-ch-bit-off" property in LLCC, according to bindings and Linux driver: qdu1000-idp.dtb: system-cache-controller@19200000: 'multi-ch-bit-off' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by:
Mukesh Ojha <quic_mojha@quicinc.com> Link: https://lore.kernel.org/r/20231107080417.16700-2-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Krzysztof Kozlowski authored
According to bindings and Linux driver there is no "multi_channel_register" address space for LLCC. The first "reg" entry is supposed to be llcc0_base since commit 43aa006e ("dt-bindings: arm: msm: Fix register regions used for LLCC banks"): qdu1000-idp.dtb: system-cache-controller@19200000: reg: [[0, 421527552, 0, 14155776], [0, 438304768, 0, 524288], [0, 572293416, 0, 4]] is too long qdu1000-idp.dtb: system-cache-controller@19200000: reg-names:0: 'llcc0_base' was expected qdu1000-idp.dtb: system-cache-controller@19200000: reg-names: ['llcc_base', 'llcc_broadcast_base', 'multi_channel_register'] is too long Signed-off-by:
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Neil Armstrong authored
Fix the following dt bindings check: arch/arm64/boot/dts/qcom/sm8450-hdk.dtb: soundwire-controller@31f0000: $nodename:0: 'soundwire-controller@31f0000' does not match '^soundwire(@.*)?$' from schema $id: http://devicetree.org/schemas/soundwire/qcom,soundwire.yaml#Signed-off-by: -
Neil Armstrong authored
Fix the following dt bindings check: arch/arm64/boot/dts/qcom/sm8550-mtp.dtb: soundwire-controller@6ab0000: $nodename:0: 'soundwire-controller@6ab0000' does not match '^soundwire(@.*)?$' from schema $id: http://devicetree.org/schemas/soundwire/qcom,soundwire.yaml#Signed-off-by:
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Bryan O'Donoghue authored
Add in CAMCC for sc8280xp. The sc8280xp Camera Clock Controller looks similar to most of the sdmX, smX and now scX controllers. Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Suggested-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by:
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Bjorn Andersson authored
Merge the SC8280XP Camera Clock Controller binding updates from the topic branch, to gain access to clock defines to be used in DeviceTree source.
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Bryan O'Donoghue authored
Add device tree bindings for the camera clock controller on Qualcomm SC8280XP platform. Signed-off-by:
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Bryan O'Donoghue authored
Various of the camcc bindings are repeated serially. We can use qcom,gcc.yaml to encapsulate the generic repeated patterns. Signed-off-by:
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Mukesh Ojha authored
Enable download mode setting for sm8550 which can help collect ramdump for this SoC. Signed-off-by:
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Mukesh Ojha authored
Enable download mode for sm8350 which can help collect ramdump for this SoC. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/1698253601-11957-3-git-send-email-quic_mojha@quicinc.comSigned-off-by:
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Mukesh Ojha authored
Enable download mode for sm8250 which can help collect ramdump for this SoC. Signed-off-by:
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Kathiravan Thirumoorthy authored
Like all other IPQ SoCs, bootloader will collect the system RAM contents upon crash for the post morterm analysis. If we don't reserve the memory region used by bootloader, obviously linux will consume it and upon next boot on crash, bootloader will be loaded in the same region, which will lead to loose some of the data, sometimes we may miss out critical information. So lets reserve the region used by the bootloader. Similarly SBL copies some data into the reserved region and it will be used in the crash scenario. So reserve 1MB for SBL as well. While at it, enable the SMEM support along with TCSR mutex. Signed-off-by:
Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Reviewed-by:
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Kathiravan Thirumoorthy authored
Add the color and function property to the GPIO LED node, which are missed out in the initial submission. Signed-off-by:
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Kathiravan Thirumoorthy authored
Add support for wlan-2g LED on GPIO64. Signed-off-by:
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Caleb Connolly authored
The default for the QCM2290 platform that this board is based on is OTG mode, however the role detection logic is not hooked up for this board and the dwc3 driver is configured to not allow role switching from userspace. Force this board to host mode as this is the preferred usecase until we get role switching hooked up. Fixes: e1877196 ("arm64: dts: qcom: Add initial QTI RB1 device tree") Signed-off-by:
Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by:
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- 03 Dec, 2023 23 commits
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Douglas Anderson authored
As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog bark interrupt edge triggered"), the Qualcomm watchdog timer's bark interrupt should be configured as edge triggered. Make the change. Fixes: 5f82b9cd ("arm64: dts: qcom: Add SM6350 device tree") Reviewed-by:Guenter Roeck <linux@roeck-us.net> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20231106144335.v2.8.Ic1d4402e99c70354d501ccd98105e908a902f671@changeidSigned-off-by:
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Douglas Anderson authored
As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog bark interrupt edge triggered"), the Qualcomm watchdog timer's bark interrupt should be configured as edge triggered. Make the change. Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform") Reviewed-by: -
Douglas Anderson authored
As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog bark interrupt edge triggered"), the Qualcomm watchdog timer's bark interrupt should be configured as edge triggered. Make the change. Fixes: 09b701b8 ("arm64: dts: qcom: sa8775p: add the watchdog node") Reviewed-by:Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20231106144335.v2.6.I909b7c4453d7b7fb0db4b6e49aa21666279d827d@changeidSigned-off-by:
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Douglas Anderson authored
As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog bark interrupt edge triggered"), the Qualcomm watchdog timer's bark interrupt should be configured as edge triggered. Make the change. Fixes: 46a4359f ("arm64: dts: qcom: sm8250: Add watchdog bark interrupt") Reviewed-by: -
Douglas Anderson authored
As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog bark interrupt edge triggered"), the Qualcomm watchdog timer's bark interrupt should be configured as edge triggered. Make the change. Fixes: b094c8f8 ("arm64: dts: qcom: sm8150: Add watchdog bark interrupt") Reviewed-by: -
Douglas Anderson authored
As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog bark interrupt edge triggered"), the Qualcomm watchdog timer's bark interrupt should be configured as edge triggered. Make the change. Fixes: 36c436b0 ("arm64: dts: qcom: sdm845: Add watchdog bark interrupt") Reviewed-by: -
Douglas Anderson authored
As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog bark interrupt edge triggered"), the Qualcomm watchdog timer's bark interrupt should be configured as edge triggered. Make the change. Fixes: 0e51f883 ("arm64: dts: qcom: sc7280: Add APSS watchdog node") Reviewed-by: -
Douglas Anderson authored
On sc7180 when the watchdog timer fires your logs get filled with: watchdog0: pretimeout event watchdog0: pretimeout event watchdog0: pretimeout event ... watchdog0: pretimeout event If you're using console-ramoops to debug crashes the above gets quite annoying since it blows away any other log messages that might have been there. The issue is that the "bark" interrupt (AKA the "pretimeout" interrupt) remains high until the watchdog is pet. Since we've got things configured as "level" triggered we'll keep getting interrupted over and over. Let's switch to edge triggered. Now we'll get one interrupt when the "bark" interrupt goes off and won't get another one until the "bark" interrupt is cleared and asserts again. This matches how many older Qualcomm SoCs have things configured. Fixes: 28cc13e4 ("arm64: dts: qcom: sc7180: Add watchdog bark interrupt") Reviewed-by:
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Krzysztof Kozlowski authored
The IOMMUs for PCI controller on SC8180x are defined in iommu-map, so drop duplicared iommus: sc8180x-lenovo-flex-5g.dtb: pci@1c08000: Unevaluated properties are not allowed ('iommus' was unexpected) Signed-off-by: -
Luca Weiss authored
Document the compatible for the MSM8926-based HTC One Mini 2 smartphone. Acked-by:
Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20231125-htc-memul-v3-2-e8f4c5839e23@z3ntu.xyzSigned-off-by:
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Luca Weiss authored
Add the vendor prefix for HTC (https://www.htc.com/). Acked-by:
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Krzysztof Kozlowski authored
The TX Soundwire controller should take clock from TX macro codec, not VA macro codec clock, otherwise the clock stays disabled. This looks like a copy-paste issue, because the SC8280xp code uses here correctly clock from TX macro. The VA macro clock is already consumed by TX macro codec, thus it won't be disabled by this change. Fixes: 61b00638 ("arm64: dts: qcom: sm8550: add Soundwire controllers") Reported-by:
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Krzysztof Kozlowski authored
The TX Soundwire controller should take clock from TX macro codec, not VA macro codec clock, otherwise the clock stays disabled. This looks like a copy-paste issue, because the SC8280xp code uses here correctly clock from TX macro. The VA macro clock is already consumed by TX macro codec, thus it won't be disabled by this change. Fixes: 14341e76 ("arm64: dts: qcom: sm8450: add Soundwire and LPASS") Reported-by:
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Bjorn Andersson authored
The hall sensor interrupt on the Primus is active low, which means that with the current configuration the device attempts to suspend when the LID is open. Fix the polarity of the HALL_INT GPIO to avoid this. Fixes: 2ce38cc1 ("arm64: dts: qcom: sc8180x: Introduce Primus") Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by:
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Johan Hovold authored
The sc8280xp Display Port PHYs can be used in either DP or eDP mode and this is configured using the devicetree compatible string which defaults to DP mode in the SoC dtsi. Override the default compatible string for the CRD eDP PHY node so that the eDP settings are used. Fixes: 4a883a8d ("arm64: dts: qcom: sc8280xp-crd: Enable EDP") Cc: stable@vger.kernel.org # 6.3 Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20231016080658.6667-1-johan+linaro@kernel.orgSigned-off-by:
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Luca Weiss authored
Enable the LPASS/ADSP found on the phone. Signed-off-by:
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Raymond Hackley authored
Acer Iconia Talk S A1-724 uses KTD2026 LED driver. However, there is no blue LED on it. Add it to the device tree. Signed-off-by:
Raymond Hackley <raymondhackley@protonmail.com> Reviewed-by:
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Robert Marko authored
IPQ6018 comes in multiple SKU-s and some of them dont support all of the OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only supported OPP-s based on the SoC dynamically. As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only goes up to 1.5GHz and is marked as such via an eFuse. Signed-off-by:
Robert Marko <robimarko@gmail.com> Reviewed-by:
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Lukas Walter authored
This dts adds support for Huawei Honor 5X / GR5 (2016) smartphone released in 2015. Add device tree with initial support for: - GPIO keys - Hall sensor - SDHCI (internal and external storage) - WCNSS (BT/WIFI) - Sensors (accelerometer and proximity) - Vibrator - Touchscreen Signed-off-by:
Lukas Walter <lukas.walter@aceart.de> Reviewed-by:
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Lukas Walter authored
Add a compatible for Huawei Honor 5X / GR5 (2016). Acked-by:
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Luca Weiss authored
Use the qcom,domain property instead of the deprecated qcom,apr-domain, which in turn also fixes a bunch of dtbs_checks warnings. Reviewed-by:
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Dmitry Baryshkov authored
The RB1 platform doesn't have board-specific board-id programmed, it uses generic 0xff. Thus add the property with the 'variant' of the calibration data. Note: the driver will check for the calibration data for the following IDs, so existing board-2.bin files will continue to work. - 'bus=snoc,qmi-board-id=ff,qmi-chip-id=120,variant=Thundercomm_RB1' - 'bus=snoc,qmi-board-id=ff,qmi-chip-id=120' - 'bus=snoc,qmi-board-id=ff' For the reference, the board is identified by the driver in the following way: ath10k_snoc c800000.wifi: qmi chip_id 0x120 chip_family 0x4007 board_id 0xff soc_id 0x40670000 ath10k_snoc c800000.wifi: qmi fw_version 0x337302d3 fw_build_timestamp 2023-01-06 01:50 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.3.3.7.c2-00723-QCAHLSWMTPLZ-1 ath10k_snoc c800000.wifi: wcn3990 hw1.0 target 0x00000008 chip_id 0x00000000 sub 0000:0000 ath10k_snoc c800000.wifi: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0 ath10k_snoc c800000.wifi: firmware ver api 5 features wowlan,mgmt-tx-by-reference,non-bmi crc32 b3d4b790 ath10k_snoc c800000.wifi: htt-ver 3.114 wmi-op 4 htt-op 3 cal file max-sta 32 raw 0 hwcrypto 1 Signed-off-by:
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Konrad Dybcio authored
Enable the Microchip mcp2518fd hosted on the SPI5 bus. Signed-off-by:
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