- 15 Jun, 2023 10 commits
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Jessica Zhang authored
Correct the math for slice_last_group_size so that it matches the calculations downstream. Fixes: c110cfd1 ("drm/msm/disp/dpu1: Add support for DSC") Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/539269/ Link: https://lore.kernel.org/r/20230329-rfc-msm-dsc-helper-v14-7-bafc7be95691@quicinc.comSigned-off-by:
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Jessica Zhang authored
The current dpu_hw_dsc calculation for det_thresh_flatness does not match the downstream calculation or the DSC spec. Use the DRM DSC helper for det_thresh_flatness to match downstream implementation and the DSC spec. Fixes: c110cfd1 ("drm/msm/disp/dpu1: Add support for DSC") Reviewed-by:
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Jessica Zhang authored
Introduce MSM-specific DSC helper methods, as some calculations are common between DP and DSC. Reviewed-by:
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Dmitry Baryshkov authored
Use new DRM DSC helpers to setup DSI DSC configuration. The initial_scale_value needs to be adjusted according to the standard, but this is a separate change. Signed-off-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by:
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Jessica Zhang authored
Add helper to get the integer value of drm_dsc_config.bits_per_pixel Reviewed-by:
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Dmitry Baryshkov authored
Add a helper setting config values which are typically constant across operating modes (table E-4 of the standard) and mux_word_size (which is a const according to 3.5.2). Signed-off-by:
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Jessica Zhang authored
Add helpers to calculate det_thresh_flatness and initial_scale_value as these calculations are defined within the DSC spec. Reviewed-by:
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Dmitry Baryshkov authored
Add definitions of DSPP blocks present on the sdm845 platform. This should enable color-management on sdm845-bassed devices. Signed-off-by:
Sumit Semwal <sumit.semwal@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/542142/ Link: https://lore.kernel.org/r/20230612182534.3345805-2-dmitry.baryshkov@linaro.org
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Dmitry Baryshkov authored
We can not support color management without DSPP blocks being provided in the HW catalog. Do not enable color management for CRTCs if num_dspps is 0. Fixes: 4259ff7a ("drm/msm/dpu: add support for pcc color block in dpu driver") Reported-by:
Yongqin Liu <yongqin.liu@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
Change adreno_is_a690() prototype to accept the const struct adreno_gpu pointer instead of a non-const one. This fixes the following warning: In file included from drivers/gpu/drm/msm/msm_drv.c:33: drivers/gpu/drm/msm/adreno/adreno_gpu.h: In function ‘adreno_is_a660_family’: drivers/gpu/drm/msm/adreno/adreno_gpu.h:303:54: warning: passing argument 1 of ‘adreno_is_a690’ discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] 303 | return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu); Fixes: 1b90e8f8 ("drm/msm/adreno: change adreno_is_* functions to accept const argument") Signed-off-by:
Rob Clark <robdclark@gmail.com> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/542138/ Link: https://lore.kernel.org/r/20230612182527.3345786-1-dmitry.baryshkov@linaro.org
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- 12 Jun, 2023 1 commit
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git://anongit.freedesktop.org/drm/drmDmitry Baryshkov authored
Merge the drm-next tree to pick up the DRM DSC helpers (merged via drm-intel-next tree). MSM DSC v1.2 patches depend on these helpers. Signed-off-by:
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- 10 Jun, 2023 10 commits
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Dmitry Baryshkov authored
All adreno_is_*() functions do not modify their argument in any way, so they can be changed to accept const struct adreno_gpu pointer. Suggested-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
Rob Clark <robdclark@chromium.org>
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Dmitry Baryshkov authored
The commit 010c8bba ("drm: msm: adreno: Disable preemption on Adreno 510") tried to check GPU's revn before revn being set. Add WARN_ON_ONCE to prevent such bugs from happening again. A separate helper is necessary so that the warning is displayed really just once instead of being displayed for each of comparisons. Suggested-by:
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Dmitry Baryshkov authored
The commit 010c8bba ("drm: msm: adreno: Disable preemption on Adreno 510") added special handling for a510 (this SKU doesn't seem to support preemption, so the driver should clamp nr_rings to 1). However the gpu->revn is not yet set (it is set later, in adreno_gpu_init()) and thus the condition is always false. Check config->rev instead. Fixes: 010c8bba ("drm: msm: adreno: Disable preemption on Adreno 510") Reported-by:
Adam Skladowski <a39.skl@gmail.com> Signed-off-by:
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Rob Clark authored
Allow access to CP_PERFCTR_CP_SEL[n] and RB_PERFCTR_RB_SEL which are used by fdperf and pps-provider (perfetto). Signed-off-by: -
Bjorn Andersson authored
Introduce support for the Adreno A690, found in Qualcomm SC8280XP. Tested-by:
Steev Klimaszewski <steev@kali.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/540335/Signed-off-by:
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Rob Clark authored
This is something that can block for arbitrary amounts of time as userspace consumes from the FIFO. So we don't really want this to be in the fence signaling path. Signed-off-by:
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Dmitry Baryshkov authored
If the Adreno SMMU is dma-coherent, allocation will fail unless we disable IO_PGTABLE_QUIRK_ARM_OUTER_WBWA. Skip setting this quirk for the coherent SMMUs (like we have on sm8350 platform). Fixes: 54af0ceb ("arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes") Reported-by:
David Heidelberg <david@ixit.cz> Signed-off-by:
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Dmitry Baryshkov authored
The variable ring is not used by msm_parse_deps() and msm_ioctl_gem_submit() and thus can be dropped. Signed-off-by:
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Dmitry Baryshkov authored
Sparse reports plenty of warnings against the a6xx code because of a6xx_gmu::mmio and a6xx_gmu::rscc members. For some reason they were defined as __iomem pointers rather than pointers to __iomem memory. Correct the __iomem attribute. Fixes: 02ef80c5 ("drm/msm/a6xx: update pdc/rscc GMU registers for A640/A650") Reported-by:
kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/oe-kbuild-all/202304070550.NrbhJCvP-lkp@intel.com/Reviewed-by:
Javier Martinez Canillas <javierm@redhat.com> Reviewed-by:
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Dmitry Baryshkov authored
Merge branches 'msm-next-lumag-core', 'msm-next-lumag-dpu', 'msm-next-lumag-dp', 'msm-next-lumag-dsi' and 'msm-next-lumag-mdp5' into msm-next-lumag Core: - Add Marijn Suijten as drm/msm reviewer - Adreno A660 bindings - SM8350 MDSS bindings fix DP: - Removed obsolete USB-PD remains - Documented DP compatible string for sm8550 platform DPU: - Added support for DPU on sm6350 and sm6375 platforms - Implemented tearcheck support to support vsync on SM150 and newer platforms - Enabled missing features (DSPP, DSC, split display) on sc8180x, sc8280xp, sm8450 - Enabled writeback on sc7280 - Enabled DSC on msm8998 - Native HDMI output support - Dropped unused features: regdma, GC, IGC - Fixed the DSC flush operations - Simplified QoS handling, removing obsolete and unused features and merging SSPP and WB code paths - Reworked dpu_encoder initialisation path DSI: - Added support for DSI and 28nm DSI PHY on MSM8226 platform - Added support for DSI on sm6350 and sm6375 platforms - Dropped powerup quirks in favour of using pre_enable_prev_first for downstream bridges - Fixed 14nm DSI PHY programming MDP5: - Added support for display controller on MSM8226 platform Signed-off-by:
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- 09 Jun, 2023 7 commits
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Dave Airlie authored
Merge tag 'drm-intel-gt-next-2023-06-08' of git://anongit.freedesktop.org/drm/drm-intel into drm-next UAPI Changes: - I915_GEM_CREATE_EXT_SET_PAT for Mesa on Meteorlake. Driver Changes: Fixes/improvements/new stuff: - Use large rings for compute contexts (Chris Wilson) - Better logging/debug of unexpected GuC communication issues (Michal Wajdeczko) - Clear out entire reports after reading if not power of 2 size (Ashutosh Dixit) - Limit lmem allocation size to succeed on SmallBars (Andrzej Hajda) - perf/OA capture robustness improvements on DG2 (Umesh Nerlige Ramappa) - Fix error code in intel_gsc_uc_heci_cmd_submit_nonpriv() (Dan Carpenter) Future platform enablement: - Add workaround 14016712196 (Tejas Upadhyay) - HuC loading for MTL (Daniele Ceraolo Spurio) - Allow user to set cache at BO creation (Fei Yang) Miscellaneous: - Use system include style for drm headers (Jani Nikula) - Drop legacy CTB definitions (Michal Wajdeczko) - Turn off the timer to sample frequencies when GT is parked (Ashutosh Dixit) - Make PMU sample array two-dimensional (Ashutosh Dixit) - Use the correct error value when kernel_context() fails (Andi Shyti) - Fix second parameter type of pre-gen8 pte_encode callbacks (Nathan Chancellor) - Fix parameter in gmch_ggtt_insert_{entries, page}() (Nathan Chancellor) - Fix size_t format specifier in gsccs_send_message() (Nathan Chancellor) - Use the fdinfo helper (Tvrtko Ursulin) - Add some missing error propagation (Tvrtko Ursulin) - Reduce I915_MAX_GT to 2 (Matt Atwood) - Rename I915_PMU_MAX_GTS to I915_PMU_MAX_GT (Matt Atwood) - Remove some obsolete definitions (John Harrison) Merges: - Merge drm/drm-next into drm-intel-gt-next (Tvrtko Ursulin) Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ZIH09fqe5v5yArsu@tursulin-desk
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git://anongit.freedesktop.org/drm/drm-intelDave Airlie authored
drm/i915 features for v6.5: Features and functionality: - Meteorlake (MTL) display enabling (Mika, Radhakrishna, José, Ankit, Clint, Gustavo, Imre, Anusha, Juha-Pekka, Matt) - Allow VRR to be toggled during fastsets (Ville) - Allow arbitrary refresh rates with VRR eDP panels (Ville) - Support async flips on linear buffers on display ver 12+ (Arun) - New debugfs for display clock frequencies (Bhanuprakash) - Taint kernel when force probing unsupported devices (Jani) - Expose CRTC CTM property on ILK/SNB/VLV (Ville) DRM subsystem changes: - EDID changes to support further conversion to struct drm_edid (Jani) - Move i915 DSC parameter code to common DRM helpers (Dmitry Baryshkov) Refactoring and cleanups: - CSC color refactoring (Ville) - VRR cleanups (Ville) - Finish i915 conversion to struct drm_edid (Jani) - Start high level display driver file (Jani) - Hotplug refactoring (Ville) - Misc display refactoring and cleanups (Jani, Ville) - Use device based logging for state checker warnings (Jani) - Split out hotplug and display irq handling (Jani) - Move display device info and probe under display/ (Matt) - HDCP cleanups (Suraj) - Use localized warning ignores instead of per file (Jani) - Remove superfluous enum i915_drm_suspend_mode (Maarten) - PSR, pfit, scaler and chicken register definition cleanups (Ville) - Constify pointers to hwmon_channel_info (Krzysztof Kozlowski) - Replace all non-returning strlcpy with strscpy (Azeem Shaikh) - Refactor VBT aux channel and DDC pin mapping (Ville) - Include cleanups (Jani) Fixes: - Fix modeset locking issue in DP MST HDCP (Suraj) - Fix disconnected Type-C/DP-alt disable at probe (Imre) - Fix HDMI PCON DSC usage and color conversions (Ankit) - Fix g4x HDMI infoframe/audio transmission port usage (Ville) - Avoid use-after-free when DP connector init fails (Maarten) - Fix voltage level for 480 MHz CDCLK (Chaitanya) - Check HPD live state during eDP probe (Ville) - Fix active port PLL selection for secondary MST streams (Imre) - Check pipe source size when using SKL+ scalers (Ville) - Fix MIPI DSI sleep sequences (Hans de Goede) - Fix DPCD register write order to match 128b/132b requirement (Arun) - Increase AUX timeout for Type-C (Suraj) - Communicate display power demands to pcode (Stan) - Fix potential division by zero in DSC compute config (Nikita Zhandarovich) - Fix fast wake AUX sync length (Jouni) - Fix potential oops on intel_get_crtc_new_encoder() (Ville) Merges: - drm-next backmerges (Rodrigo, Jani) Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for v6.5: UAPI Changes: Cross-subsystem Changes: Core Changes: Driver Changes: * bridge * imx: Fix module linking * tc358762: Support reset GPIO * meson * Add support for MIPI DSI displays; plus fixes and DT bindings * panel * Add Support for Rocktech RK043FN48H; plus DT bindings * Add support for Starry himax83102-j02; plus DT bindings * Add support for Starry ili9882t; plus DT bindings * virtio * Support sync-object UAPI Signed-off-by:
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Dave Airlie authored
Merge tag 'drm-habanalabs-next-2023-06-08' of https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/linux into drm-next This tag contains additional habanalabs driver changes for v6.5: - uAPI changes: - Return 0 when user queries if there was a h/w or f/w error and no such error happened. Previously we returned an error in such case. - New features and improvements: - Add pci health check when we lose connection with the firmware. This can be used to distinguish between pci link down and firmware getting stuck. - Add more info to the error print when TPC interrupt occur. - Reduce amount of code under mutex in the command submission of signal event. - Firmware related fixes: - Fixes to the handshake protocol during f/w initialization. - Display information that the f/w sends us when encountering a DMA error. - Do soft-reset using a message sent to firmware instead of writing to MMIO. - Prepare generic code to extract f/w version numbers. - Bug fixes and code cleanups. Notable fixes are: - Unsecure certain TPC registers that the user should access. - Fix handling of QMAN errors - Fix memory leak when recording errors (to later pass them to the user) - Multiple fixes to razwi interrupt handling code Signed-off-by:
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Dave Airlie authored
Merge tag 'drm-next-20230529' of git://git.kernel.org/pub/scm/linux/kernel/git/pinchartl/linux into drm-next Renesas DRM/KMS drivers: - Group drivers in renesas subdirectory to prepare for new platform - Drop deprecated R-Car H3 ES1.x support Signed-off-by:
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Dmitry Baryshkov authored
Move GMU mutex initialization earlier to make sure that it is always initialized. a6xx_destroy can be called from ther failure path before GMU initialization. This fixes the following backtrace: ------------[ cut here ]------------ DEBUG_LOCKS_WARN_ON(lock->magic != lock) WARNING: CPU: 0 PID: 58 at kernel/locking/mutex.c:582 __mutex_lock+0x1ec/0x3d0 Modules linked in: CPU: 0 PID: 58 Comm: kworker/u16:1 Not tainted 6.3.0-rc5-00155-g187c06436519 #565 Hardware name: Qualcomm Technologies, Inc. SM8350 HDK (DT) Workqueue: events_unbound deferred_probe_work_func pstate: 60400005 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : __mutex_lock+0x1ec/0x3d0 lr : __mutex_lock+0x1ec/0x3d0 sp : ffff800008993620 x29: ffff800008993620 x28: 0000000000000002 x27: ffff47b253c52800 x26: 0000000001000606 x25: ffff47b240bb2810 x24: fffffffffffffff4 x23: 0000000000000000 x22: ffffc38bba15ac14 x21: 0000000000000002 x20: ffff800008993690 x19: ffff47b2430cc668 x18: fffffffffffe98f0 x17: 6f74616c75676572 x16: 20796d6d75642067 x15: 0000000000000038 x14: 0000000000000000 x13: ffffc38bbba050b8 x12: 0000000000000666 x11: 0000000000000222 x10: ffffc38bbba603e8 x9 : ffffc38bbba050b8 x8 : 00000000ffffefff x7 : ffffc38bbba5d0b8 x6 : 0000000000000222 x5 : 000000000000bff4 x4 : 40000000fffff222 x3 : 0000000000000000 x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff47b240cb1880 Call trace: __mutex_lock+0x1ec/0x3d0 mutex_lock_nested+0x2c/0x38 a6xx_destroy+0xa0/0x138 a6xx_gpu_init+0x41c/0x618 adreno_bind+0x188/0x290 component_bind_all+0x118/0x248 msm_drm_bind+0x1c0/0x670 try_to_bring_up_aggregate_device+0x164/0x1d0 __component_add+0xa8/0x16c component_add+0x14/0x20 dsi_dev_attach+0x20/0x2c dsi_host_attach+0x9c/0x144 devm_mipi_dsi_attach+0x34/0xac lt9611uxc_attach_dsi.isra.0+0x84/0xfc lt9611uxc_probe+0x5b8/0x67c i2c_device_probe+0x1ac/0x358 really_probe+0x148/0x2ac __driver_probe_device+0x78/0xe0 driver_probe_device+0x3c/0x160 __device_attach_driver+0xb8/0x138 bus_for_each_drv+0x84/0xe0 __device_attach+0x9c/0x188 device_initial_probe+0x14/0x20 bus_probe_device+0xac/0xb0 deferred_probe_work_func+0x8c/0xc8 process_one_work+0x2bc/0x594 worker_thread+0x228/0x438 kthread+0x108/0x10c ret_from_fork+0x10/0x20 irq event stamp: 299345 hardirqs last enabled at (299345): [<ffffc38bb9ba61e4>] put_cpu_partial+0x1c8/0x22c hardirqs last disabled at (299344): [<ffffc38bb9ba61dc>] put_cpu_partial+0x1c0/0x22c softirqs last enabled at (296752): [<ffffc38bb9890434>] _stext+0x434/0x4e8 softirqs last disabled at (296741): [<ffffc38bb989669c>] ____do_softirq+0x10/0x1c ---[ end trace 0000000000000000 ]--- Fixes: 4cd15a3e ("drm/msm/a6xx: Make GPU destroy a bit safer") Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by:
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Kuogee Hsieh authored
The internal_hpd flag is set to true by dp_bridge_hpd_enable() and set to false by dp_bridge_hpd_disable() to handle GPIO pinmuxed into DP controller case. HDP related interrupts can not be enabled until internal_hpd is set to true. At current implementation dp_display_config_hpd() will initialize DP host controller first followed by enabling HDP related interrupts if internal_hpd was true at that time. Enable HDP related interrupts depends on internal_hpd status may leave system with DP driver host is in running state but without HDP related interrupts being enabled. This will prevent external display from being detected. Eliminated this dependency by moving HDP related interrupts enable/disable be done at dp_bridge_hpd_enable/disable() directly regardless of internal_hpd status. Changes in V3: -- dp_catalog_ctrl_hpd_enable() and dp_catalog_ctrl_hpd_disable() -- rewording ocmmit text Changes in V4: -- replace dp_display_config_hpd() with dp_display_host_start() -- move enable_irq() at dp_display_host_start(); Changes in V5: -- replace dp_display_host_start() with dp_display_host_init() Changes in V6: -- squash remove enable_irq() and disable_irq() Fixes: cd198cad ("drm/msm/dp: Rely on hpd_enable/disable callbacks") Signed-off-by:
Kuogee Hsieh <quic_khsieh@quicinc.com> Tested-by: Leonard Lausen <leonard@lausen.nl> # on sc7180 lazor Reviewed-by:
Bjorn Andersson <andersson@kernel.org> Tested-by:
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- 08 Jun, 2023 12 commits
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Dani Liberman authored
Moved error info reset code to single function for future use from other places in the driver. Signed-off-by:
Dani Liberman <dliberman@habana.ai> Reviewed-by:
Oded Gabbay <ogabbay@kernel.org> Signed-off-by:
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Ofir Bitton authored
In order to increase reliability of the event queue interface, we apply to Gaudi2 the same mechanism we have in Gaudi1. The extra validation is basically checking that the received event index matches the expected index. Signed-off-by:
Ofir Bitton <obitton@habana.ai> Reviewed-by:
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Ofir Bitton authored
In order to utilize Engine Barrier padding, user must have access to this register set. Signed-off-by:
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Oded Gabbay authored
We don't want to allow users to spam the kernel log and sending ioctls with bad opcodes is a sure way to do it. Signed-off-by:
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Ofir Bitton authored
addr_dec info should always be fetched, regardless of cause value. Signed-off-by:
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Dani Liberman authored
Several info ioctls may return success although no data retrieved. Signed-off-by:
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Oded Gabbay authored
There were a few places where simulator only code got into the upstream. Remove those places that can confuse other developers. Fixes: 2a0a839b ("habanalabs: extend fatal messages to contain PCI info") Cc: Moti Haimovski <mhaimovski@habana.ai> Cc: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by:
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Dani Liberman authored
When receiving page fault from hmmu, the captured address is scrambled both by HW and by driver. The driver part is unscrambled but the HW part isn't getting unscrambled. To avoid declaring wrong address, the HW scrambled part will be masked. Signed-off-by:
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Koby Elbaz authored
Any FW component we load must be followed by a corresponding state update. However, it seems that so far we skipped doing so for the bootfit case, so fix that. Signed-off-by:
Koby Elbaz <kelbaz@habana.ai> Reviewed-by:
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Tomer Tayar authored
By default, the upper QMANs are not used, and instead engines ARCs access the lower QMANs directly. Errors for upper QMANs are therefore not expected, and the debug print of the PQ entries is not needed. Modify the QMAN debug data print on errors to include only information for the lower QMAN. Signed-off-by:
Tomer Tayar <ttayar@habana.ai> Reviewed-by:
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Tomer Tayar authored
The QMAN GLBL_ERR_STS_4 register has indications for errors also in the lower CQ and the ARC CQ, and not just for errors in the lower CP. Modify the relevant define/struct and the related print to use "lower QM" instead of "lower CP". Signed-off-by:
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Dani Liberman authored
When receiving sei interrupt from tpc or decoder, we need to check the binning mask because if the engine is binned, the razwi info won't be in the router of the binned engine, instead will be in the router of the substitute engine. Signed-off-by:
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