- 19 May, 2011 1 commit
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Michal Marek authored
The timestamps recorded in the .gz files add no value. Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by:
Michal Marek <mmarek@suse.cz> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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- 06 May, 2011 7 commits
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Jack Miller authored
Signed-off-by:
Jack Miller <jack@codezen.org> Signed-off-by:
Michael Ellerman <michael@ellerman.id.au> Signed-off-by:
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David Gibson authored
Add a platform for the Wire Speed Processor, based on the PPC A2. This includes code for the ICS & OPB interrupt controllers, as well as a SCOM backend, and SCOM based cpu bringup. Signed-off-by:
David Gibson <david@gibson.dropbear.id.au> Signed-off-by:
Ian Munsie <imunsie@au1.ibm.com> Signed-off-by:
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Richard A Lary authored
For adapters which have devices under a PCIe switch/bridge it is informative to display information for both the PCIe switch/bridge and the device on which the bus error was detected. rebased to powerpc-next Signed-off-by:
Richard A Lary <rlary@linux.vnet.ibm.com> Signed-off-by:
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Benjamin Herrenschmidt authored
slb0_limit() wasn't a very descriptive name. This changes it along with a comment explaining what it's used for, and provides a 64-bit BookE implementation. Signed-off-by: -
Tseng-Hui (Frank) Lin authored
This patch adds support for handling IO Event interrupts which come through at the /event-sources/ibm,io-events device tree node. The interrupts come through ibm,io-events device tree node are generated by the firmware to report IO events. The firmware uses the same interrupt to report multiple types of events for multiple devices. Each device may have its own event handler. This patch implements a plateform interrupt handler that is triggered by the IO event interrupts come through ibm,io-events device tree node, pull in the IO events from RTAS and call device event handlers registered in the notifier list. Device event handlers are expected to use atomic_notifier_chain_register() and atomic_notifier_chain_unregister() to register/unregister their event handler in pseries_ioei_notifier_list list with IO event interrupt. Device event handlers are responsible to identify if the event belongs to the device event handler. The device event handle should return NOTIFY_OK after the event is handled if the event belongs to the device event handler, or NOTIFY_DONE otherwise. Signed-off-by:
Tseng-Hui (Frank) Lin <thlin@us.ibm.com> Signed-off-by:
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Tseng-Hui (Frank) Lin authored
This patch adds definitions of non-IBM specific v6 extended log definitions to rtas.h. Signed-off-by:
Tseng-Hui (Frank) Lin <tsenglin@us.ibm.com> Signed-off-by:
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Stephen Rothwell authored
Due to a collision between NO_CONTEXT->MMU_NO_CONTEXT change and Anton's patch. Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
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- 04 May, 2011 11 commits
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Robert P. J. Day authored
Remove the unnecessary initialization of "dev_t bsr_dev" since it's subsequently used in an "alloc_chrdev_region()" call which uses that variable in an output-only fashion. Signed-off-by:
Robert P. J. Day <rpjday@crashcourse.ca> Signed-off-by:
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Richard A Lary authored
Fundamental reset is an optional reset type supported only by PCIe adapters. Handle the unexpected case where a non-PCIe device has requested a fundamental reset. Try hot-reset as a fallback to handle this case. Signed-off-by:
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Richard A Lary authored
For multifunction adapters with a PCI bridge or switch as the device at the Partitionable Endpoint(PE), if one or more devices below PE sets dev->needs_freset, that value will be set for the PE device. In other words, if any device below PE requires a fundamental reset the PE will request a fundamental reset. Signed-off-by:
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Brian King authored
Adds support for page coalescing, which is a feature on IBM Power servers which allows for coalescing identical pages between logical partitions. Hint text pages as coalesce candidates, since they are the most likely pages to be able to be coalesced between partitions. This patch also exports some page coalescing statistics available from firmware via lparcfg. [BenH: Moved a couple of things around to fix compile problems] Signed-off-by:
Brian King <brking@linux.vnet.ibm.com> Signed-off-by:
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Ben Hutchings authored
Commit b987812b left crash_kexec_wait_realmode() undefined for UP. Commit 7c7a81b5 defined it for UP but left it undefined for 32-bit SMP. Seems like people are getting confused by nested #ifdef's, so move the definitions of crash_kexec_wait_realmode() after the #ifdef CONFIG_SMP section. Compile-tested with 32-bit UP, 32-bit SMP and 64-bit SMP configurations. Signed-off-by:
Ben Hutchings <ben@decadent.org.uk> Tested-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
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KOSAKI Motohiro authored
Adapt new API. Almost change is trivial. Most important change is the below line because we plan to change task->cpus_allowed implementation. - ctx->cpus_allowed = current->cpus_allowed; Signed-off-by:
KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com> Signed-off-by:
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Paul Mackerras authored
Recent 64-bit server processors (POWER6 and POWER7) have a "Come-From Address Register" (CFAR), that records the address of the most recent branch or rfid (return from interrupt) instruction for debugging purposes. This saves the value of the CFAR in the exception entry code and stores it in the exception frame. We also make xmon print the CFAR value in its register dump code. Rather than extend the pt_regs struct at this time, we steal the orig_gpr3 field, which is only used for system calls, and use it for the CFAR value for all exceptions/interrupts other than system calls. This means we don't save the CFAR on system calls, which is not a great problem since system calls tend not to happen unexpectedly, and also avoids adding the overhead of reading the CFAR to the system call entry path. Signed-off-by:
Paul Mackerras <paulus@samba.org> Signed-off-by:
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Paul Mackerras authored
When we take an interrupt or exception from kernel mode and the stack pointer is obviously not a kernel address (i.e. the top bit is 0), we switch to an emergency stack, save register values and panic. However, on 64-bit server machines, we don't actually save the values of r9 - r13 at the time of the interrupt, but rather values corrupted by the exception entry code for r12-r13, and nothing at all for r9-r11. This fixes it by passing a pointer to the register save area in the paca through to the bad_stack code in r3. The register values are saved in one of the paca register save areas (depending on which exception this is). Using the pointer in r3, the bad_stack code now retrieves the saved values of r9 - r13 and stores them in the exception frame on the emergency stack. This also stores the normal exception frame marker ("regshere") in the exception frame. Signed-off-by: -
Tseng-Hui (Frank) Lin authored
Icswx is a PowerPC instruction to send data to a co-processor. On Book-S processors the LPAR_ID and process ID (PID) of the owning process are registered in the window context of the co-processor at initialization time. When the icswx instruction is executed the L2 generates a cop-reg transaction on PowerBus. The transaction has no address and the processor does not perform an MMU access to authenticate the transaction. The co-processor compares the LPAR_ID and the PID included in the transaction and the LPAR_ID and PID held in the window context to determine if the process is authorized to generate the transaction. The OS needs to assign a 16-bit PID for the process. This cop-PID needs to be updated during context switch. The cop-PID needs to be destroyed when the context is destroyed. Signed-off-by:
Sonny Rao <sonnyrao@linux.vnet.ibm.com> Signed-off-by:
Tseng-Hui (Frank) Lin <thlin@linux.vnet.ibm.com> Signed-off-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
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Michael Neuling authored
This removes MMU_FTR_TLBIE_206 as we can now use CPU_FTR_HVMODE_206. It also changes the logic to select which tlbie to use to be based on this new CPU feature bit. This also duplicates the ASM_FTR_IF/SET/CLR defines for CPU features (copied from MMU features). Signed-off-by:
Michael Neuling <mikey@neuling.org> Signed-off-by:
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Grant Likely authored
First step in eliminating irq_map[] table entirely Signed-off-by:
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- 27 Apr, 2011 21 commits
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Richard A. Lary authored
Added support for ibm,configure-pe RTAS call introduced with PAPR 2.2. Signed-off-by:
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Matt Evans authored
Some of the 64bit PPC CPU features are MMU-related, so this patch moves them to MMU_FTR_ bits. All cpu_has_feature()-style tests are moved to mmu_has_feature(), and seven feature bits are freed as a result. Signed-off-by:
Matt Evans <matt@ozlabs.org> Signed-off-by:
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Anton Blanchard authored
RTAS returns extended error codes as a hint of how long the OS might want to wait before retrying a call. If we have nothing else useful to do we may as well call back straight away. This was found when testing the new dynamic dma window feature. Firmware split the zeroing of the TCE table into 32k chunks but returned 9901 (which is a suggested wait of 10ms). All up this took about 10 minutes to complete since msleep is jiffies based and will round 10ms up to 20ms. With the patch below we take 3 seconds to complete the same test. The hint firmware is returning in the RTAS call should definitely be decreased, but even if we slept 1ms each iteration this would take 32s. Signed-off-by:
Nishanth Aravamudan <nacc@us.ibm.com> Signed-off-by:
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Michael Ellerman authored
The calculation of the size for the exception save area of the TLB miss handler is wrong, luckily it's too big not too small. Rework it to make it a bit clearer, and also correct. We want 3 save areas, each EX_TLB_SIZE _bytes_. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
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Michael Ellerman authored
We check MSR_SF a lot in sstep.c, to decide if we need to emulate the truncation of values when running in 32-bit mode. Factor out that code into a helper, and convert it and the other uses to use MSR_64BIT. This fixes a bug on BOOK3E where kprobes would end up returning to a 32-bit address, because regs->nip was truncated, because (msr & MSR_SF) was false. Signed-off-by:
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Michael Ellerman authored
Use the new MSR_64BIT in a few places. Some of these are already ifdef'ed for BOOKE vs BOOKS, but it's still clearer, MSR_SF does not immediately parse as "MSR bit for 64bit". Signed-off-by:
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Michael Ellerman authored
The MSR bit which indicates 64-bit-ness is different between server and booke, so add a #define which gives you the right mask regardless. Signed-off-by:
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Wanlong Gao authored
BT_L2CAP and BT_SCO have changed to bool . Value 'm' has invalid . Signed-off-by:
Wanlong Gao <wanlong.gao@gmail.com> Signed-off-by:
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Geert Uytterhoeven authored
commit ec775d0e ("powerpc: Convert to new irq_* function names") changed a call from set_irq_chip_data() to irq_set_chip_data(), but forgot to update the corresponding debug message Signed-off-by:
Geert Uytterhoeven <geert@linux-m68k.org> Acked-by:
Geoff Levand <geoff@infradead.org> Signed-off-by:
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Michael Ellerman authored
This can be useful for differentiating interrupts on the same host but with different chip data. Signed-off-by:
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Michael Ellerman authored
If we don't find ibm,associativity-reference-points as a child of /rtas, look for it at the root of the tree instead. We use this on Book3E where we have no RTAS but still use the sPAPR conventions for NUMA. Signed-off-by:
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Michael Ellerman authored
Even when no initfunc is provided. Signed-off-by:
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Michael Ellerman authored
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Michael Ellerman authored
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Michael Ellerman authored
The goal is to avoid adding overhead to MMIO when only PIO is needed Signed-off-by:
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Nishanth Aravamudan authored
Commit fe3cc0d9 ("powerpc: Add pgprot_writecombine") in benh's tree exposes the pgprot_writecombine() API to drivers on powerpc. cxgb4 has an open-coded version of the same, so use the common API now that it's available. Signed-off-by:
Steve Wise <swise@opengridcomputing.com> Signed-off-by:
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Alexey Kardashevskiy authored
The DSCR (aka Data Stream Control Register) is supported on some server PowerPC chips and allow some control over the prefetch of data streams. This patch allows the value to be specified per thread by emulating the corresponding mfspr and mtspr instructions. Children of such threads inherit the value. Other threads use a default value that can be specified in sysfs - /sys/devices/system/cpu/dscr_default. If a thread starts with non default value in the sysfs entry, all children threads inherit this non default value even if the sysfs value is changed later. Signed-off-by:
Alexey Kardashevskiy <aik@au1.ibm.com> Signed-off-by:
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Jack Miller authored
When we set up the TLB for ourselves on Book3E, we need to flush out any old mappings established by the firmware or bootloader. At present we attempt this with a tlbilx to flush everything, but this will leave behind any entries with the IPROT bit set. There are several good reason firmware might establish mappings with IPROT, and in fact ePAPR compliant firmwares are required to establish their initial mapped area with IPROT. This patch, therefore adds more complex code to scan through the TLB upon entry and flush away any entries that are not our own. Signed-off-by:
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Benjamin Herrenschmidt authored
An erratum on A2 can lead to the bolted entry we insert for the linear mapping being evicted, to avoid that write the bolted entry to way 3. Signed-off-by:
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Michael Ellerman authored
In exc_lvl_ctx_init() we index into the crit/dbg/mcheck stacks using the hard cpu id, but that assumes the hard cpu id is zero based and contiguous. That is not the case on A2. The root of the problem is that the 32bit code has no equivalent of the paca to allow it to do the hard->soft mapping in assembler. Until the 32bit code is updated to handle that, index the stacks using the soft cpu ids on 64bit and hard on 32 bit. Signed-off-by:
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Benjamin Herrenschmidt authored
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