- 09 May, 2014 8 commits
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Heiko Stübner authored
Introduce the syscons for grf and pmu and deprecate the previous register areas. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Tested-by:
Max Schwarz <max.schwarz@online.de> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Heiko Stübner authored
This allows the basic registers of the general register files to be supplied by a syscon instead of being mapped locally. The GRF registers contain a lot more than pinctrl functions like dma, usb-phy and general soc control and status registers, intermixed with the iomux, pull and drive-strength registers. Signed-off-by:
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Heiko Stübner authored
When the pmu registers are supplied through a syscon regmap we do not need to map the registers ourself. Signed-off-by:
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Heiko Stübner authored
Currently the pmu registers containing pin pull settings on the rk3188 are mapped locally when bank0 is instantiated. Add an alternative that can resolve the pmu from a syscon phandle. Signed-off-by:
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Heiko Stübner authored
Convert rockchip_get_bank_data to use the struct rockchip_pinctrl because later on we need to check a value from it when registering the gpio banks. Signed-off-by:
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Heiko Stübner authored
This allows us to use syscons in the future. Signed-off-by:
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Heiko Stübner authored
Deprecate secondary register area for rk3188 pulls. Instead use big enough initial mapping of grf registers to catch all. The now deprecated register is still supported though. Signed-off-by:
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https://github.com/mripard/linuxLinus Walleij authored
Pinctrl cleanup and reworks for 3.16 This serie of patch: - Moves the Allwinner pinctrl driver to a folder of its own - removes the sunxi-pinctrl-pins header, and split the driver into a core one, with all the logic, and smaller drivers, one for each SoC, that declare the pins, and will provide to the core the set of pins. - And does a few cleanups here and there.
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- 05 May, 2014 2 commits
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Maxime Ripard authored
The way that reset is handled right now is that it is made optional for every pinctrl driver, while actually, it isn't used at all for the main pin controllers so far, and while it's mandatory for the A31's secondary pin controller. Move the reset functions out of the core and in the driver, where they can be made mandatory. Signed-off-by:Maxime Ripard <maxime.ripard@free-electrons.com>
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Maxime Ripard authored
Add one Kconfig option for each driver. This will allow to better control which driver is enabled, instead of having either all or nothing. Signed-off-by:
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- 04 May, 2014 12 commits
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Maxime Ripard authored
Move the pin description to a driver specific to be. This is the final step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. We can finally remove that header, and remove all the driver part of the pinctrl-sunxi core. Signed-off-by: -
Maxime Ripard authored
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: -
Maxime Ripard authored
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: -
Maxime Ripard authored
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: -
Maxime Ripard authored
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: -
Maxime Ripard authored
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: -
Maxime Ripard authored
This will allow to have multiple drivers using the same core code, and eventually, retire pinctrl-sunxi-pins.h Signed-off-by: -
Maxime Ripard authored
The previous code was calling of_iomap, which doesn't do any resource management, and doesn't call request_mem_region either. Use devm_ioremap_resource that do both. Signed-off-by: -
Maxime Ripard authored
We previously had an evergrowing (and exhaustive) list of the pins that could be used on any Allwinner SoCs. These defines were then used by each pinctrl driver to declare the list of functions for this pin. Since it's pretty much all boilerplate, we can remove it just by a single macro. Signed-off-by: -
Maxime Ripard authored
This will allow to create numerous files without crippling the main pinctrl directory. Signed-off-by: -
Maxime Ripard authored
The ranges and nranges were never used. Remove them. Signed-off-by: -
Maxime Ripard authored
The pins description structure were declared as const, but the of_device_id data magic was losing it silently. Make sure we have it on both sides. And now that we're using const, we can also remove the useless cast in probe. Signed-off-by:
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- 02 May, 2014 1 commit
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Andy Gross authored
Fix copy/paste error in pinctrl_pin_desc for pin 0. Signed-off-by:
Andy Gross <agross@codeaurora.org> Signed-off-by:
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- 24 Apr, 2014 1 commit
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Thomas Petazzoni authored
This commit extends the pinctrl mvebu logic with a new driver to cover Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281 variants of Orion5x, which are the three ones supported by the old style MPP code in arch/arm/mach-orion5x/. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by:
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- 23 Apr, 2014 9 commits
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Heiko Stübner authored
In some cases it is nice to be able to simply control a gpio output via the PIN_CONFIG_OUTPUT option without having a driver control it. Thus add support for it to the rockchip pinctrl driver. Signed-off-by:
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Heiko Stübner authored
Till now pinconf_get only set the argument value into the config parameter effectively removing the actual config param value. As other pinctrl drivers do, it might be nicer to keep the config param intact. Therefore construct a real pinconfig value from param and arg in pinconf_get Signed-off-by:
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Linus Walleij authored
This switches the SiRF pinctrl driver over to using the gpiolib irqchip helpers simplifying some of the code. Signed-off-by:
Barry Song <Baohua.Song@csr.com> Signed-off-by:
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Barry Song authored
all gpio banks are in one chip, that makes software clean in mapping irq and gpio. Signed-off-by:
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Linus Walleij authored
The sirfsoc_irqchip_to_bank() is obviously misnamed, as it is not converting an irqchip to a bank but converts a gpiochip to a bank so rename it sirfsoc_gpiochip_to_bank(). Acked-by:
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Andy Gross authored
Define a new binding for the Qualcomm TLMMv2 based pin controller inside the IPQ8064. Signed-off-by:
Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by:
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Andy Gross authored
This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the Qualcomm IPQ8064 platform. Signed-off-by:
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Boris BREZILLON authored
List all sunxi pinctrl compatible strings in order to be able to grep for those values. Signed-off-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by:
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Tomasz Figa authored
This patch adds driver data (bank list and EINT layout) for Exynos3250 to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output ports. There are 23 general port groups. Changes from v1: - Add signed-off of sender - Post only separated patch for pinctrl from following patchset(v1) : https://lkml.org/lkml/2014/4/10/286 Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Chanwoo Choi <cw00.choi@samsung.com> Acked-by:
Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by:
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- 22 Apr, 2014 7 commits
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Alexander Stein authored
pin_to_mask expects a bank pin number. So do not add the chip base. Without that patch cat /sys/kernel/debug/gpio looks like that: GPIOs 0-31, platform/fffff200.gpio, fffff200.gpio: [spi32766.0] GPIOfffff200.gpio5: [gpio] set [ads7846_pendown] GPIOfffff200.gpio15: [gpio] set [ohci_vbus] GPIOfffff200.gpio21: [gpio] set [ohci_vbus] GPIOfffff200.gpio24: [gpio] set [button1] GPIOfffff200.gpio28: [gpio] clear [button2] GPIOfffff200.gpio29: [gpio] clear GPIOs 32-63, platform/fffff400.gpio, fffff400.gpio: [sda] GPIOfffff400.gpio4: [periph A] [scl] GPIOfffff400.gpio5: [periph A] [spi32766.3] GPIOfffff400.gpio11: [periph A] [error] GPIOfffff400.gpio22: [periph A] [run] GPIOfffff400.gpio23: [periph A] GPIOs 64-95, platform/fffff600.gpio, fffff600.gpio: [reset_pin] GPIOfffff600.gpio29: [periph A] GPIOs 96-127, platform/fffff800.gpio, fffff800.gpio: [led1] GPIOfffff800.gpio5: [periph A] [led2] GPIOfffff800.gpio6: [periph A] [led3] GPIOfffff800.gpio7: [periph A] [led4] GPIOfffff800.gpio8: [periph A] GPIOs 128-159, platform/fffffa00.gpio, fffffa00.gpio: [button3] GPIOfffffa00.gpio10: [periph A] [button4] GPIOfffffa00.gpio12: [periph A] Note that every bank despite bank 0 only shows "periph A" which are obviously used as GPIOs. Signed-off-by:
Alexander Stein <alexanders83@web.de> Acked-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
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Alexander Stein authored
This converts the AT91 pin control driver to register its chained irq handler and irqchip using the helpers in the gpiolib core. Signed-off-by:
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Stephen Warren authored
The kerneldoc for struct tegra_pingroup didn't describe all of the fields in the struct. Add some extra kerneldoc to fix that. Signed-off-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
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Stephen Warren authored
When an attempt is made to configure an unsupported option on a pin, print the DT property name of that option, so it's easier to debug what the problem is. Signed-off-by:
Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by:
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Stephen Warren authored
The range of npins and function ID values is small enough to fit into a u8. Use this type rather than unsigned to shrink the pinmux data tables. Signed-off-by:
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Stephen Warren authored
The fsafe value in the pingroup data tables is only used to implement tegra_pinctrl_disable(). The only reason this function is called is when dynamically switching between pinmux states, i.e. when disabling the old state before programming the new state. It's simpler to have the new target state define the expected value of each pin (and all current DTs do that). This also gives more flexibility, since it allows individual boards explicit control over the "inactive" mux function for each pin, rather than requiring it to be an SoC-specific value. Assuming this, we can get rid of the fsafe value from the driver completely, thus saving some more space in the driver tables. While re-writing the content of tegra124_pingroups[], fix the indentation to use a TAB instead of spaces. Signed-off-by:
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Stephen Warren authored
Any SoC which supports the einput, odrain, lock, ioreset, or rcv_sel options has the relevant HW register fields in the same register as the mux function selection. Similarly, the drvtype option is always in the drive register, if it is supported at all. Hence, we don't need to have struct *_reg fields in the pin group table to define which register and bank to use for those options. Delete this to save space in the driver's data tables. However, many of those options are not supported on all SoCs, or not supported on some pingroups. We need a way to detect when they are supported. Previously, this was indicated by setting the struct *_reg field to -1. With the struct *_reg fields removed, we use the struct *_bit fields for this purpose instead. The struct *_bit fields need to be expanded from 5 to 6 bits in order to store a value outside the valid HW bit range of 0..31. Even without removing the struct *_reg fields, we still need to add code to validate the struct *_bit fields, since some struct *_bit fields were already being set to -1, without an option-specific struct *_reg field to "guard" them. In other words, before this change, the pinmux driver might allow some unsupported options to be written to HW. Signed-off-by:
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