1. 04 Oct, 2019 32 commits
  2. 03 Oct, 2019 8 commits
    • Eric Dumazet's avatar
      net: propagate errors correctly in register_netdevice() · 9077f052
      Eric Dumazet authored
      If netdev_name_node_head_alloc() fails to allocate
      memory, we absolutely want register_netdevice() to return
      -ENOMEM instead of zero :/
      
      One of the syzbot report looked like :
      
      general protection fault: 0000 [#1] PREEMPT SMP KASAN
      CPU: 1 PID: 8760 Comm: syz-executor839 Not tainted 5.3.0+ #0
      Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011
      RIP: 0010:ovs_vport_add+0x185/0x500 net/openvswitch/vport.c:205
      Code: 89 c6 e8 3e b6 3a fa 49 81 fc 00 f0 ff ff 0f 87 6d 02 00 00 e8 8c b4 3a fa 4c 89 e2 48 b8 00 00 00 00 00 fc ff df 48 c1 ea 03 <80> 3c 02 00 0f 85 d3 02 00 00 49 8d 7c 24 08 49 8b 34 24 48 b8 00
      RSP: 0018:ffff88808fe5f4e0 EFLAGS: 00010247
      RAX: dffffc0000000000 RBX: ffffffff89be8820 RCX: ffffffff87385162
      RDX: 0000000000000000 RSI: ffffffff87385174 RDI: 0000000000000007
      RBP: ffff88808fe5f510 R08: ffff8880933c6600 R09: fffffbfff14ee13c
      R10: fffffbfff14ee13b R11: ffffffff8a7709df R12: 0000000000000004
      R13: ffffffff89be8850 R14: ffff88808fe5f5e0 R15: 0000000000000002
      FS:  0000000001d71880(0000) GS:ffff8880ae900000(0000) knlGS:0000000000000000
      CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
      CR2: 0000000020000280 CR3: 0000000096e4c000 CR4: 00000000001406e0
      DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
      DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
      Call Trace:
       new_vport+0x1b/0x1d0 net/openvswitch/datapath.c:194
       ovs_dp_cmd_new+0x5e5/0xe30 net/openvswitch/datapath.c:1644
       genl_family_rcv_msg+0x74b/0xf90 net/netlink/genetlink.c:629
       genl_rcv_msg+0xca/0x170 net/netlink/genetlink.c:654
       netlink_rcv_skb+0x177/0x450 net/netlink/af_netlink.c:2477
       genl_rcv+0x29/0x40 net/netlink/genetlink.c:665
       netlink_unicast_kernel net/netlink/af_netlink.c:1302 [inline]
       netlink_unicast+0x531/0x710 net/netlink/af_netlink.c:1328
       netlink_sendmsg+0x8a5/0xd60 net/netlink/af_netlink.c:1917
       sock_sendmsg_nosec net/socket.c:637 [inline]
       sock_sendmsg+0xd7/0x130 net/socket.c:657
       ___sys_sendmsg+0x803/0x920 net/socket.c:2311
       __sys_sendmsg+0x105/0x1d0 net/socket.c:2356
       __do_sys_sendmsg net/socket.c:2365 [inline]
       __se_sys_sendmsg net/socket.c:2363 [inline]
       __x64_sys_sendmsg+0x78/0xb0 net/socket.c:2363
      
      Fixes: ff927412 ("net: introduce name_node struct to be used in hashlist")
      Signed-off-by: default avatarEric Dumazet <edumazet@google.com>
      Cc: Jiri Pirko <jiri@mellanox.com>
      Reported-by: default avatarsyzbot <syzkaller@googlegroups.com>
      Tested-by: default avatarWillem de Bruijn <willemb@google.com>
      Reviewed-by: default avatarJiri Pirko <jiri@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      9077f052
    • David S. Miller's avatar
      Merge branch 'phy-at803x-add-ar9331-support' · 6964773e
      David S. Miller authored
      Oleksij Rempel says:
      
      ====================
      phy: at803x: add ar9331 support
      
      changes v3:
      - use PHY_ID_MATCH_EXACT only for ATH9331 PHY
      
      changes v2:
      - use PHY_ID_MATCH_EXACT instead of leaky masking
      - remove probe and struct at803x_priv
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      6964773e
    • Oleksij Rempel's avatar
      net: phy: at803x: remove probe and struct at803x_priv · 7271df0b
      Oleksij Rempel authored
      struct at803x_priv is never used in this driver. So remove it
      and the probe function allocating it.
      Suggested-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
      Signed-off-by: default avatarOleksij Rempel <o.rempel@pengutronix.de>
      Reviewed-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      7271df0b
    • Oleksij Rempel's avatar
      net: phy: at803x: add ar9331 support · 7908d2ce
      Oleksij Rempel authored
      Mostly this hardware can work with generic PHY driver, but this change
      is needed to provided interrupt handling support.
      Tested with dsa ar9331-switch driver.
      Signed-off-by: default avatarOleksij Rempel <o.rempel@pengutronix.de>
      Reviewed-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      7908d2ce
    • Petr Machata's avatar
      mlxsw: PCI: Send EMAD traffic on a separate queue · 6aaee55c
      Petr Machata authored
      Currently mlxsw distributes sent traffic among all the available send
      queues. That includes control traffic as well as EMADs, which are used for
      configuration of the device.
      
      However because all the queues have the same traffic class of 3, they all
      end up being directed to the same traffic class buffer. If the control
      traffic in the buffer cannot be serviced quickly enough, the EMAD traffic
      might be shut out, which causes transient failures, typically in FDB
      maintenance, counter upkeep and other periodic work.
      
      To address this issue, dedicate SDQ 0 to EMAD traffic, with TC 0.
      Distribute the control traffic among the remaining queues, which are left
      with their current TC 3.
      Suggested-by: default avatarIdo Schimmel <idosch@mellanox.com>
      Signed-off-by: default avatarPetr Machata <petrm@mellanox.com>
      Acked-by: default avatarJiri Pirko <jiri@mellanox.com>
      Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      6aaee55c
    • Ka-Cheong Poon's avatar
      net/rds: Use DMA memory pool allocation for rds_header · 9b17f588
      Ka-Cheong Poon authored
      Currently, RDS calls ib_dma_alloc_coherent() to allocate a large piece
      of contiguous DMA coherent memory to store struct rds_header for
      sending/receiving packets.  The memory allocated is then partitioned
      into struct rds_header.  This is not necessary and can be costly at
      times when memory is fragmented.  Instead, RDS should use the DMA
      memory pool interface to handle this.  The DMA addresses of the pre-
      allocated headers are stored in an array.  At send/receive ring
      initialization and refill time, this arrary is de-referenced to get
      the DMA addresses.  This array is not accessed at send/receive packet
      processing.
      Suggested-by: default avatarHåkon Bugge <haakon.bugge@oracle.com>
      Signed-off-by: default avatarKa-Cheong Poon <ka-cheong.poon@oracle.com>
      Acked-by: default avatarSantosh Shilimkar <santosh.shilimkar@oracle.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      9b17f588
    • David S. Miller's avatar
      Merge branch 'stmmac-eam' · df1025fc
      David S. Miller authored
      Thierry Reding says:
      
      ====================
      net: stmmac: Enhanced addressing mode for DWMAC 4.10
      
      The DWMAC 4.10 supports the same enhanced addressing mode as later
      generations. Parse this capability from the hardware feature registers
      and set the EAME (Enhanced Addressing Mode Enable) bit when necessary.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      df1025fc
    • Thierry Reding's avatar
      net: stmmac: Support enhanced addressing mode for DWMAC 4.10 · 560c07cb
      Thierry Reding authored
      The address width of the controller can be read from hardware feature
      registers much like on XGMAC. Add support for parsing the ADDR64 field
      so that the DMA mask can be set accordingly.
      
      This avoids getting swiotlb involved for DMA on Tegra186 and later.
      
      Also make sure that the upper 32 bits of the DMA address are written to
      the DMA descriptors when enhanced addressing mode is used. Similarily,
      for each channel, the upper 32 bits of the DMA descriptor ring's base
      address also need to be programmed to make sure the correct memory can
      be fetched when the DMA descriptor ring is located beyond the 32-bit
      boundary.
      Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      560c07cb