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- 21 Nov, 2014 1 commit
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Yijing Wang authored
Save MSI controller in pci_sys_data instead of assigning MSI controller pointer to every PCI bus in .add_bus(). Signed-off-by:
Yijing Wang <wangyijing@huawei.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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- 13 Nov, 2014 1 commit
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Jingoo Han authored
This patch fixes the following checkpatch warning: WARNING: Missing a blank line after declarations [bhelgaas: drop mvebu_pcie_add_bus() change because it's going away anyway] Signed-off-by:
Jingoo Han <jg1.han@samsung.com> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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- 12 Nov, 2014 1 commit
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Yijing Wang authored
"msi_chip" isn't very descriptive, so rename it to "msi_controller". That tells a little more about what it does and is already used in device tree bindings. No functional change. [bhelgaas: changelog, change *only* the struct name so it's reviewable] Suggested-by:
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- 22 Sep, 2014 1 commit
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Thomas Petazzoni authored
Geert Uytterhoeven reported a warning when building pci-mvebu: drivers/pci/host/pci-mvebu.c: In function 'mvebu_get_tgt_attr': drivers/pci/host/pci-mvebu.c:887:39: warning: 'rtype' may be used uninitialized in this function [-Wmaybe-uninitialized] if (slot == PCI_SLOT(devfn) && type == rtype) { ^ And indeed, the code of mvebu_get_tgt_attr() may lead to the usage of rtype when being uninitialized, even though it would only happen if we had entries other than I/O space and 32 bits memory space. This commit fixes that by simply skipping the current DT range being considered, if it doesn't match the resource type we're looking for. Reported-by:Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
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- 15 Jul, 2014 1 commit
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Thierry Reding authored
Per license_is_gpl_compatible(), the MODULE_LICENSE() string for GPL v2 is "GPL v2", not "GPLv2". Use "GPL v2" so this module doesn't taint the kernel. [bhelgaas: changelog] Signed-off-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
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- 11 Jun, 2014 1 commit
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Ryan Desfosses authored
Fix various whitespace errors. No functional change. [bhelgaas: fix other similar problems] Signed-off-by:
Ryan Desfosses <ryan@desfo.org> Signed-off-by:
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- 29 Apr, 2014 2 commits
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Fabio Estevam authored
Fix the following build warning that happens when building multi_v7_defconfig with CONFIG_ARM_LPAE=y: drivers/pci/host/pci-mvebu.c:334:5: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'phys_addr_t' [-Wformat=] Fix the warning by using '%pa' to printing 'phys_addr_t' type. While at it, also use the more standard notation [mem 0x-0x] for memory region. [bhelgaas: make end address inclusive, remove extra spaces] Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
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Andrew Murray authored
Serialization of configuration accesses is provided by 'pci_lock' in drivers/pci/access.c thus making the driver's 'conf_lock' superfluous. Signed-off-by:
Andrew Murray <amurray@embedded-bits.co.uk> Signed-off-by:
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- 24 Apr, 2014 2 commits
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Thomas Petazzoni authored
MBus windows are used on Marvell platforms to map certain peripherals in the physical address space. In the PCIe context, MBus windows are needed to map PCIe I/O and memory regions in the physical address. However, those MBus windows can only have power of two sizes, while PCIe BAR do not necessarily guarantee this. For this reason, the current pci-mvebu breaks on platforms where PCIe devices have BARs that don't sum up to a power of two size at the emulated bridge level. This commit fixes this by allowing the pci-mvebu driver to create multiple contiguous MBus windows (each having a power of two size) to cover a given PCIe BAR. To achieve this, two functions are added: mvebu_pcie_add_windows() and mvebu_pcie_del_windows() to respectively add and remove all the MBus windows that are needed to map the provided PCIe region base and size. The emulated PCI bridge code now calls those functions, instead of directly calling the mvebu-mbus driver functions. Fixes: 45361a4f ('pci: PCIe driver for Marvell Armada 370/XP systems') Cc: <stable@vger.kernel.org> # v3.11+ Signed-off-by:
Neil Greatorex <neil@fatboyfat.co.uk> Acked-by:
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Willy Tarreau authored
mvebu_pcie_handle_membase_change() and mvebu_pcie_handle_iobase_change() do not correctly compute the window size. PCI uses an inclusive start/end address pair, which requires a +1 when converting to size. This only worked because a bug in the mbus driver allowed it to silently accept and round up bogus sizes. Fix this by adding one to the computed size. Fixes: 45361a4f ('PCIe driver for Marvell Armada 370/XP systems') Cc: <stable@vger.kernel.org> # v3.11+ Signed-off-by:
Willy Tarreau <w@1wt.eu> Reviewed-By:
Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by:
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- 18 Feb, 2014 1 commit
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Jason Gunthorpe authored
It is typical for host drivers to request a resource for the aperture; once this is done the PCI core will properly populate resources for all BARs in the system. With this patch cat /proc/iomem will now show: e0000000-efffffff : PCI MEM 0000 e0000000-e00fffff : PCI Bus 0000:01 e0000000-e001ffff : 0000:01:00.0 Tested on Kirkwood. Signed-off-by:Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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- 14 Feb, 2014 1 commit
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Jean-Jacques Hiblot authored
The second parameter of of_read_number() is not the index, but a size. As it happens, in this case it may work just fine because of the conversion to u32 and the favorable endianness on this architecture. Fixes: 11be6547 ("PCI: mvebu: Adapt to the new device tree layout") Tested-by:
Jean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by:
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- 12 Feb, 2014 2 commits
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Andrew Lunn authored
Marvell SoCs place the SoC number into the PCIe endpoint device ID. The SoC stepping is placed into the PCIe revision. The old plat-orion PCIe driver allowed this information to be seen in user space with a simple lspci command. The new driver places a virtual PCI-PCI bridge on top of these endpoints. It has its own hard coded PCI device ID. Thus it is no longer possible to see what the SoC is using lspci. When initializing the PCI-PCI bridge, set its device ID and revision from the underlying endpoint, thus restoring this functionality. Debian would like to use this in order to aid installing the correct DTB file. Fixes: 45361a4f ("pci: PCIe driver for Marvell Armada 370/XP systems") Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
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Andrew Lunn authored
Marvell SoCs place the SoC number into the PCIe endpoint device ID. The SoC stepping is placed into the PCIe revision. The old plat-orion PCIe driver allowed this information to be seen in user space with a simple lspci command. The new driver places a virtual PCI-PCI bridge on top of these endpoints. It has its own hard coded PCI device ID. Thus it is no longer possible to see what the SoC is using lspci. When initializing the PCI-PCI bridge, set its device ID and revision from the underlying endpoint, thus restoring this functionality. Debian would like to use this in order to aid installing the correct DTB file. Fixes: 45361a4f ("pci: PCIe driver for Marvell Armada 370/XP systems") Signed-off-by:
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- 02 Jan, 2014 2 commits
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Jingoo Han authored
Use max_t() instead of max(resource_size_t,) in order to fix the following checkpatch warning. WARNING: max() should probably be max_t(resource_size_t, SZ_64K, size) WARNING: max() should probably be max_t(resource_size_t, SZ_1M, size) Signed-off-by:
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Thomas Petazzoni authored
The mvebu PCI host controller driver uses an emulated PCI-to-PCI bridge to leverage the core PCI kernel enumeration logic to dynamically create and remove the MBus windows needed to access the memory and I/O regions of each PCI interface. In the context of this PCI-to-PCI bridge emulation, the driver emulates all reads and writes to the PCI bridge registers. Upon a write to the registers configuring the I/O base and limit, the driver was creating the MBus window and calling pci_ioremap_io() to setup the mapping. However, it turns out that accesses to these registers are made in an IRQ disabled context, while pci_ioremap_io() is a potentially sleeping function. Not only this is wrong, but it is causing fairly loud warnings at boot time when the appropriate kernel hacking options are enabled. This patch solves this by moving the pci_ioremap_io() call to the startup of the driver. At this point, we don't know how many PCI interfaces will be enabled, so we are simply remapping the entire PCI I/O space to virtual addresses. This is reasonable since this I/O space is limited to 1 MB in size, and also because the MBus windows continue to be created in a dynamic fashion only when devices need them. Signed-off-by:
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- 19 Dec, 2013 1 commit
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Sachin Kamat authored
mvebu_pcie_of_match_table is always compiled in. Hence of_match_ptr is not required. Signed-off-by:
Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by:
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- 09 Dec, 2013 1 commit
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Andrew Lunn authored
Probably due to a merge conflict resolution gone bad, the PCI clock is got twice. Remove the redundant call of of_clk_get_by_name(). Signed-off-by:
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- 26 Nov, 2013 4 commits
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Jason Gunthorpe authored
Make pcie-io-aperture and the IO port MBUS ID in ranges optional. If not provided the bridge reports to Linux that IO space mapping is not supported and refuses to configure an IO MBUS window. This allows both complete disable (do not specify pcie-io-aperture) and per-port disable (do not specify a IO target ranges entry for the port). Most PCIe devices these days do not require IO support to function, so having an option to disable it in the driver is useful. Tested-by:
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Jason Gunthorpe authored
When PCI_COMMAND_MEMORY/PCI_COMMAND_IO are cleared, the bridge should not allocate windows or even look at the window limit/base registers. Otherwise we may set up bogus windows while the PCI core code performs discovery. The core will leave PCI_COMMAND_IO cleared if it doesn't need an IO window. Have mvebu_pcie_handle_*_change respect the bits, and call the change function whenever the bits changes. Tested-by:
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Jason Gunthorpe authored
The emulated bridge does not support interrupts, so it should return the value 0 for Interrupt Line and Interrupt Pin. This indicates that interrupts are not supported. Since Max_Lat and Min_Gnt are also in the same 32-bit word, we return 0 for them, which means "do not care." This corrects an error message from the kernel: pci 0000:00:01.0: of_irq_parse_pci() failed with rc=135 Which is due to the default return of 0xFFFFFFFF indicating that interrupts are supported. The error message regression was caused by 16b84e5a ("of/irq: Create of_irq_parse_and_map_pci() to consolidate arch code.") Signed-off-by:
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Jason Gunthorpe authored
There are no writable bits in the secondary status register, only RO and RW1C (write-1-to-clear) bits. The driver never sets any of the RW1C bits, so the status register should always be 0, just remove the set from the write path. Someday the RW1C bits should be copied/cleared directly from registers in the HW. [bhelgaas: changelog tweaks] Signed-off-by:
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- 24 Oct, 2013 4 commits
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Grant Likely authored
Several architectures open code effectively the same code block for finding and mapping PCI irqs. This patch consolidates it down to a single function. Signed-off-by:
Grant Likely <grant.likely@linaro.org> Acked-by:
Michal Simek <monstr@monstr.eu> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Grant Likely authored
All the callers of irq_create_of_mapping() pass the contents of a struct of_phandle_args structure to the function. Since all the callers already have an of_phandle_args pointer, why not pass it directly to irq_create_of_mapping()? Signed-off-by:
Tony Lindgren <tony@atomide.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Grant Likely authored
struct of_irq and struct of_phandle_args are exactly the same structure. This patch makes the kernel use of_phandle_args everywhere. This in itself isn't a big deal, but it makes some follow-on patches simpler. Signed-off-by:
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Grant Likely authored
The OF irq handling code has been overloading the term 'map' to refer to both parsing the data in the device tree and mapping it to the internal linux irq system. This is probably because the device tree does have the concept of an 'interrupt-map' function for translating interrupt references from one node to another, but 'map' is still confusing when the primary purpose of some of the functions are to parse the DT data. This patch renames all the of_irq_map_* functions to of_irq_parse_* which makes it clear that there is a difference between the parsing phase and the mapping phase. Kernel code can make use of just the parsing or just the mapping support as needed by the subsystem. The patch was generated mechanically with a handful of sed commands. Signed-off-by:
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- 08 Oct, 2013 3 commits
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Jingoo Han authored
mvebu_pcie_add_bus(), mvebu_pcie_align_resource() are used only in this file. Thus, these local functions should be staticized in order to fix the following sparse warnings: drivers/pci/host/pci-mvebu.c:684:6: warning: symbol 'mvebu_pcie_add_bus' was not declared. Should it be static? drivers/pci/host/pci-mvebu.c:690:17: warning: symbol 'mvebu_pcie_align_resource' was not declared. Should it be static? Signed-off-by:
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Seungwon Jeon authored
This change adds wrapper functions for MMIO access to PCIe IP block. And some 8/16-bit access are replaced by 32-bit. Signed-off-by:
Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by:
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Jason Gunthorpe authored
Otherwise hotplugging the PEX doesn't work at all since the driver detects the link state at probe time. Simply replacing the two tests of haslink with a register read is enough to fix it. Tested on kirkwood with repeated plug/unplug of the link partner. Signed-off-by:
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- 30 Sep, 2013 6 commits
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Sebastian Hesselbarth authored
This patch adds a compatible for the PCIe controller found on Marvell Dove SoCs. Binding documentation and Kconfig entry are also updated. Signed-off-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by:
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Sebastian Hesselbarth authored
This patch adds a check for DT passed reset-gpios property and deasserts/ asserts reset pin on probe/remove with configurable delay. Corresponding binding documentation is also updated. Signed-off-by:
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Sebastian Hesselbarth authored
This removes the subsys_initcall from the driver and converts it to a normal platform_driver. Also, drvdata is set and a remove functions is added to disable the clock and free resources. As pci driver removal currently is not supported, set .suppress_bind_attrs to permit unbinding. Signed-off-by:
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Sebastian Hesselbarth authored
The number of ports is probed by counting the number of available child nodes. Later on, the registration of a port can fail and cause a mismatch between the ->nports counter and registered ports. This patch modifies the counting strategy, to make ->nports represent the number of registered ports instead of the number of available childs. Signed-off-by:
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Sebastian Hesselbarth authored
The clock passed to PCI controller found on MVEBU SoCs may come from a clock gate. This requires the clock to be enabled before any registers are accessed. Therefore, move the clock enable before register iomap to ensure it is enabled. Signed-off-by:
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Thomas Petazzoni authored
This commit adds support for Message Signaled Interrupts in the Marvell PCIe host controller. The work is very simple: it simply gets a reference to the msi_chip associated to the PCIe controller thanks to the msi-parent DT property, and stores this reference in the pci_bus structure. This is enough to let the Linux PCI core use the functions of msi_chip to setup and teardown MSIs. Signed-off-by:
Thierry Reding <thierry.reding@gmail.com> Acked-by:
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- 06 Aug, 2013 3 commits
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Tushar Behera authored
Commit 75096579 ("lib: devres: Introduce devm_ioremap_resource()") introduced devm_ioremap_resource() and deprecated the use of devm_request_and_ioremap(). While at it, modify mvebu_pcie_map_registers() to propagate error code. Signed-off-by:
Tushar Behera <tushar.behera@linaro.org> Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Ezequiel Garcia authored
This driver does not fail to probe when it cannot obtain a port base address. Therefore, add a check for NULL base address before setting up the port, which prevents a kernel panic in such cases. Signed-off-by:
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Thomas Petazzoni authored
The new device tree layout encodes the window's target ID and attribute in the PCIe controller node's ranges property. This allows to parse such entries to obtain such information and use the recently introduced MBus API to create the windows, instead of using the current name based scheme. Acked-by:
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- 01 Aug, 2013 1 commit
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Thomas Petazzoni authored
The Marvell PCIe driver uses an emulated PCI-to-PCI bridge to be able to dynamically set up MBus address decoding windows for PCI I/O and memory regions depending on the PCI devices enumerated by Linux. However, this emulated PCI-to-PCI bridge logic makes the Linux PCI core believe that prefetchable memory regions are supported (because the registers are read/write), while in fact no adress decoding window is ever created for such regions. Since the Marvell MBus address decoding windows do not distinguish memory regions and prefetchable memory regions, this patch takes a simple approach: change the PCI-to-PCI bridge emulation to let the Linux PCI core know that we don't support prefetchable memory regions. To achieve this, we simply make the prefetchable memory base a read-only register that always returns 0. Reading/writing all the other prefetchable memory related registers has no effect. This problem was originally reported by Finn Hoffmann <finn@uni-bremen.de>, who couldn't get a RTL8111/8168B PCI NIC working on the NSA310 Kirkwood platform after updating to 3.11-rc. The problem was that the PCI-to-PCI bridge emulation was making the Linux PCI core believe that we support prefetchable memory, so the Linux PCI core was only filling the prefetchable memory base and limit registers, which does not lead to a MBus window being created. The below patch has been confirmed by Finn Hoffmann to fix his problem on Kirkwood, and has otherwise been successfully tested on the Armada XP GP platform with a e1000e PCIe NIC and a Marvell SATA PCIe card. Reported-by:
Finn Hoffmann <finn@uni-bremen.de> Signed-off-by:
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- 27 May, 2013 1 commit
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Thomas Petazzoni authored
We allow the pci-mvebu driver to be compiled on the Kirkwood platform, and add the 'marvell,kirkwood-pcie' as a compatible string supported by the driver. Signed-off-by:
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