- 06 May, 2010 29 commits
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Cyril Chemparathy authored
The earlier watchdog reset mechanism had a couple of limitations. First, it embedded a reference to "davinci_wdt_device" inside common code. This forced all derived platforms (da8xx and tnetv107x) to define such a device. This also would have caused problems in including multiple socs in a single build due to symbol redefinition. With this patch, davinci_watchdog_reset() now takes the platform device as an argument. The davinci_soc_info struct has been extended to include a reset function and a watchdog platform_device. arch_reset() then uses these elements to reset the system in a SoC specific fashion. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Tested-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Cyril Chemparathy authored
Pinmux registers are sequential, and do not need to be enumerated out as they currently are. This reduces code volume and keeps things simple. If some future SoC comes up with a discontiguous register map, PINMUX() can then be expanded with local token pasting. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Cyril Chemparathy authored
This patch eliminates the global gpio_lock, and implements a per-controller lock instead. This also switches to irqsave/irqrestore locks in case gpios are manipulated in isr. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Tested-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Cyril Chemparathy authored
This patch allows for gpio controllers that deviate from those found on traditional davinci socs. davinci_soc_info has an added field to indicate the soc-specific gpio controller type. The gpio initialization code then bails out if necessary. More elements (tnetv107x) to be added later into enum davinci_gpio_type. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Tested-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Cyril Chemparathy authored
This patch renders the inlined gpio accessors in gpio.h independent of the underlying controller's register layout. This is done by including three new fields in davinci_gpio_controller to hold the addresses of the set, clear, and in data registers. Other changes: 1. davinci_gpio_regs structure definition moved to gpio.c. This structure is no longer common across all davinci socs (davinci_gpio_controller is). 2. controller base address calculation code (gpio2controller()) moved to gpio.c as this was no longer necessary for the inline implementation. 3. modified inline range checks to use davinci_soc_info.gpio_num instead of DAVINCI_N_GPIO. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Tested-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Cyril Chemparathy authored
Renamed gpio types to something more sensible: struct gpio_controller --> struct davinci_gpio_regs struct davinci_gpio --> struct davinci_gpio_controller gpio2controller() --> gpio2regs() irq2controller() --> irq2regs() This change also moves davinci_gpio_controller definition to gpio.h. Eventually, the gpio registers structure will be moved to gpio.c and no longer a common cross-soc definition. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Tested-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Cyril Chemparathy authored
macroized repeated container_of()s to improve readability. unified direction in/out functions. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Tested-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sergei Shtylyov authored
The IDE platform device is registered in three different places (2 board files for DM644x and in dm646x.c for DM646x) while both the IDE base address and the IDE IRQ are the same for both SoCs -- therefore, the proper place for the IDE platform seems to be in devices.c. Merge the IDE platform data and registration code and create davinci_init_ide() in place of dm646x_init_ide()... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Thomas Koeller authored
linux/compiler.h is required for __iomem linux/types.h is required u32 Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Cyril Chemparathy authored
This patch allows socs to override the divider ratio mask by setting an optional field (div_ratio_mask) in the pll_data structure. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Tested-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Thomas Koeller authored
Extended the MUX configuration to allow use of GPIO terminals 64..57. Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sergei Shtylyov authored
The board file #define's its own version of EMIFA base addresses, while there are DA8XX_AEMIF_*_BASE macros #define'd in <mach/da8xx.h>. Start using them instead. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sergei Shtylyov authored
Currently each DaVinci board file #define's its own version of the EMIFA base addresses (all named DAVINCI_ASYNC_EMIF_*_BASE), which leads to duplication. Move these #define's to the SoC specific headers, changing their prefixes from 'DAVINCI' to the 'DM355', 'DM644X', and 'DM646X' since all these base addresses are SoC specific... And while at it, rename DM646X_ASYNC_EMIF_DATA_CE0_BASE to DM646X_ASYNC_EMIF_CS2_SPACE_BASE in order to match the DM646x datasheet. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Cyril Chemparathy authored
Added tnetv107x cpu type definitions and cpu identification macros. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Cyril Chemparathy authored
IRQ numbers as defined for tnetv107x cp_intc. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Cyril Chemparathy authored
Added definitions for LPSC modules in the tnetv107x SOC Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Cyril Chemparathy authored
Added list of muxed pins on the tnetv107x SOC. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Cyril Chemparathy authored
Rename da8xx_pinmux_setup() to davinci_cfg_reg_list() and promote it for use in other SOCs that may need the ability to configure multiple pins in one shot. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Cyril Chemparathy authored
The current clock control code always gates the clock (PSC state Disable = 2) on clk_disable(). Some on-chip peripherals (e.g. LCD controller on TNETV107X) need to be put into SwRstDisable = 0 on clock disable, to maintain hardware sanity. This patch extends the davinci_psc_config() arguments to pass in the desired module state instead of a boolean enable/disable. Further, clk_disable() now checks for the PSC_SWRSTDISABLE clk flag before selecting the target state. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Cyril Chemparathy authored
Host map configuration instructs the interrupt controller to route interrupt channels to FIQ or IRQ lines. Currently, DA8xx family of devices leave these registers at their reset-default values. TNETV107X however does not have sane reset defaults, and therefore this architecture needs to reconfigure the host-map such that channels 0 and 1 go to FIQ, and the remaining channels raise IRQs. This patch adds an optional host map argument to cp_intc_init() for this. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Cyril Chemparathy authored
timer_init() programs timer64 hardware. The module should ideally be brought out of reset before this happens. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Cyril Chemparathy authored
Preliminary modification prior to adding support for TNETV107X based on ARM1176. This change allows for CPUs other than ARM926T to be used for Davinci derivative SoCs. Existing devices (DA8x and DMx) operate unchanged. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sekhar Nori authored
The rtc-omap driver currently hardcodes the RTC wakeup capability to be "not capable". While this seems to be true for existing OMAP1 boards which are not wired for this, the DA850/OMAP-L138 SoC, the RTC can always be wake up source from its "deep sleep" mode. This patch lets the wakeup capability to be set from platform data and does not override the setting from the driver. For DA850/OMAP-L138, this is done from arch/arm/mach-davinci/devices-da8xx.c:da8xx_register_rtc() Note that this patch does not change the behavior on any existing OMAP1 board since the platform device registration sets the wakeup capability to 0 by default. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Miguel Aguilar authored
This driver features: * Alarm support. * Periodic interrupt by using a timer include into the RTC module. * The update interrupt is not supported by this RTC module. This driver was tested on a DM365 EVM by using the rtc-test application from the Documentation/rtc.txt. Signed-off-by: Miguel Aguilar <miguel.aguilar@ridgerun.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Acked-by: Alessandro Zummo <a.zummo@towertech.it>
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Anuj Aggarwal authored
Currently, the ISR in the EDMA driver clears the pending interrupt for all channels without regard to whether that channel has a registered callback or not. This causes problems for devices like DM355/DM365 where the multimedia accelerator uses EDMA by polling on the interrupt pending bits of some of the EDMA channels. Since these channels are actually allocated through the Linux EDMA driver (by an out-of-kernel module), the same shadow region is used by Linux and accelerator. There a race between the Linux ISR and the polling code running on the accelerator on the IPR (interrupt pending register). This patch fixes the issue by making the ISR clear the interrupts only for those channels which have interrupt enabled. The channels which are allocated for the purpose of being polled on by the accelerator will not have a callback function provided and so will not have IER (interrupt enable register) bits set. Tested on DM365 and OMAP-L137/L138 with audio and MMC/SD (as EDMA users). Signed-off-by: Anuj Aggarwal <anuj.aggarwal@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> CC: Archith John Bency <archith@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Vipin Bhandari authored
The merge for 2.6.34 brings in 8-bit support to the DaVinci MMC/SD driver. This patch updates the platform data for DA830/OMAP-L137 EVM to use 8-wire support available in the driver. Signed-off-by: Vipin Bhandari <vipin.bhandari@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Vipin Bhandari authored
The DA830/OMAP-L137 EVM has GPIO based card detection logic, but the current code does not use it. Add support for GPIO based card detection to avoid reading the card to see if a card is present or not. Signed-off-by: Vipin Bhandari <vipin.bhandari@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Kevin Hilman authored
Cleanup usage of void pointers when using genirq. genirq API takes and returns void *, where this GPIO API is using those as __iomem pointers. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Kevin Hilman authored
- Convert data/functions to static - include headers for missing declarations - pointer cleanups: struct foo *__iomem f --> struct foo __iomem *f; Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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- 30 Apr, 2010 7 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/jwessel/linux-2.6-kgdbLinus Torvalds authored
* 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jwessel/linux-2.6-kgdb: kgdb: don't needlessly skip PAGE_USER test for Fsl booke
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git://oss.sgi.com/xfs/xfsLinus Torvalds authored
* 'for-linus' of git://oss.sgi.com/xfs/xfs: xfs: add a shrinker to background inode reclaim
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Wufei authored
The bypassing of this test is a leftover from 2.4 vintage kernels, and is no longer appropriate, or even used by KGDB. Currently KGDB uses probe_kernel_write() for all access to memory via the KGDB core, so it can simply be deleted. This fixes CVE-2010-1446. CC: Benjamin Herrenschmidt <benh@kernel.crashing.org> CC: Paul Mackerras <paulus@samba.org> CC: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Wufei <fei.wu@windriver.com> Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
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git://git.kernel.dk/linux-2.6-blockLinus Torvalds authored
* 'for-linus' of git://git.kernel.dk/linux-2.6-block: exofs: Fix "add bdi backing to mount session" fall out fs: fs/super.c needs to include backing-dev.h for !CONFIG_BLOCK
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Linus Torvalds authored
* master.kernel.org:/home/rmk/linux-2.6-arm: ARM: 6061/1: PL061 GPIO: Bug fix - setting gpio for HIGH_LEVEL interrupt is not working. ARM: 5957/1: ARM: RealView SD/MMC Card detection and write-protect using GPIOLIB ARM: 6030/1: KS8695: enable console ARM: 6060/1: PL061 GPIO: Setting gpio val after changing direction to OUT. ARM: 6059/1: PL061 GPIO: Changing *_irq_chip_data with *_irq_data for real irqs. ARM: 6023/1: update bcmring_defconfig to latest version and fix build error ARM: fix build error in arch/arm/kernel/process.c
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git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpcLinus Torvalds authored
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: powerpc/ps3: Update ps3_defconfig powerpc/ps3: Update platform maintainer powerpc/pseries: Flush lazy kernel mappings after unplug operations powerpc/numa: Add form 1 NUMA affinity powerpc/fsl-booke: Fix CONFIG_RELOCATABLE support on FSL Book-E ppc32 powerpc: 2.6.34 update of defconfigs for embedded 6xx/7xxx, 8xx, 8xxx powerpc/mpc8xxx defconfigs - turn off SYSFS_DEPRECATED powerpc/83xx: configure SIL SATA driver in 83xx-wide defconfig powerpc/83xx: enable EPOLL syscall in defconfig powerpc/83xx: add RTC drivers in 83xx defconfig powerpc/fsl-cpm: Configure clock correctly for SCC powerpc/fsl_booke: Correct test for MMU_FTR_BIG_PHYS powerpc/85xx/86xx: Fix build w/ CONFIG_PCI=n
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- 29 Apr, 2010 4 commits
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viresh kumar authored
In current implementation of PL061, setting type of irq to HIGH_LEVEL is not working. This patch fixes this bug. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Dave Chinner authored
On low memory boxes or those with highmem, kernel can OOM before the background reclaims inodes via xfssyncd. Add a shrinker to run inode reclaim so that it inode reclaim is expedited when memory is low. This is more complex than it needs to be because the VM folk don't want a context added to the shrinker infrastructure. Hence we need to add a global list of XFS mount structures so the shrinker can traverse them. Signed-off-by: Dave Chinner <dchinner@redhat.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
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Boaz Harrosh authored
The patch: add bdi backing to mount session (b3d0ab7e) Has a bug in the placement of the bdi member at struct exofs_sb_info. The layout member must be kept last. Signed-off-by: Boaz Harrosh <bharrosh@panasas.com> Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
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Jens Axboe authored
When CONFIG_BLOCK is set, it ends up getting backing-dev.h included. But for !CONFIG_BLOCK, it isn't so lucky. The proper thing to do is include <linux/backing-dev.h> directly from the file it's used from, so do that. Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
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