- 08 Apr, 2019 5 commits
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Dan Carpenter authored
The address of "ipctl->pin_regs[pin_id]" can't be NULL. It's the offset into an array in the middle of a struct. This patch removes the check. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Acked-by:
Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Zhiyong Tao authored
This patch provides the advanced drive for I2C used pins on MT8183. The detail strength specification description of the I2C pin: When E1=0/E0=0, the strength is 0.125mA. When E1=0/E0=1, the strength is 0.25mA. When E1=1/E0=0, the strength is 0.5mA. When E1=1/E0=1, the strength is 1mA. For I2C pins, there are existing generic driving setup and the above specific driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA driving adjustment in generic driving setup. But in specific driving setup, they can support 0.125/0.25/0.5/1mA adjustment. If we enable specific driving setup for I2C pins, the existing generic driving setup will be disabled. For some special features, we need the I2C pins specific driving setup. The specific driving setup is controlled by E1E0EN. So we need add extra vendor driving preperty instead of the generic driving property. We can add "mediatek,drive-strength-adv = <XXX>;" to describe the specific driving setup property. "XXX" means the value of E1E0EN. So the valid arguments of "mediatek,drive-strength-adv" are from 0 to 7. Signed-off-by:
Zhiyong Tao <zhiyong.tao@mediatek.com> Signed-off-by:
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Zhiyong Tao authored
The commit adds mt8183 compatible node in binding document. Signed-off-by:
Erin Lo <erin.lo@mediatek.com> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Aditya Pakki authored
axp20x_build_funcs_groups allocates groups via devm_kcalloc and tries to dereference without checking for NULL. This patch avoids such a scenario. Signed-off-by:
Aditya Pakki <pakki001@umn.edu> Signed-off-by:
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Linus Walleij authored
EXPORT_SYMBOL_GPL() needs a semicolon at the end, also explicitly include <linux/export.h> as well. Fixes: 64ebde5b ("gpiolib: export devprop_gpiochip_set_names()") Acked-by:
Jan Kundrát <jan.kundrat@cesnet.cz> Signed-off-by:
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- 04 Apr, 2019 12 commits
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YueHaibing authored
Fix sparse warnings: drivers/pinctrl/pinctrl-artpec6.c:691:5: warning: symbol 'artpec6_pmx_enable' was not declared. Should it be static? drivers/pinctrl/pinctrl-artpec6.c:705:6: warning: symbol 'artpec6_pmx_disable' was not declared. Should it be static? Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Acked-by:
Jesper Nilsson <jesper.nilsson@axis.com> Reviewed-by:
Mukesh Ojha <mojha@codeaurora.org> Signed-off-by:
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Linus Walleij authored
Merge tag 'sh-pfc-for-v5.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.2 - Add HSCIF (serial) pin groups on R-Car H1, - Add I2C[035] pin groups on R-Car M3-N, - Add CANFD pin groups on RZ/G2M and RZ/G2E, - Retain SDHI/MMC clock return path delay configuration across suspend/resume on R-Car Gen3, - More validation of pinmux tables at build and runtime, including compile-test coverage of all drivers, - Small fixes, improvements, and cleanups.
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Takeshi Kihara authored
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. [takeshi.kihara.df: add blank lines after function declarations] Signed-off-by:Takeshi Kihara <takeshi.kihara.df@renesas.com> [uli: use standard macros PINMUX_IPSR_PHYS and PINMUX_IPSR_PHYS_MSEL] Signed-off-by:
Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Ulrich Hecht authored
Pin data for I2C controllers 0, 3 and 5 is properly defined already. Signed-off-by:
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Geert Uytterhoeven authored
Replace "F_(0,0)" by "F_(0, 0)". Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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YueHaibing authored
Fix sparse warning: drivers/pinctrl/freescale/pinctrl-scu.c:38:19: warning: symbol 'pinctrl_ipc_handle' was not declared. Should it be static? Signed-off-by:
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Charles Keepax authored
Lochnagar is an evaluation and development board for Cirrus Logic Smart CODEC and Amp devices. It allows the connection of most Cirrus Logic devices on mini-cards, as well as allowing connection of various application processor systems to provide a full evaluation platform. This driver supports the board controller chip on the Lochnagar board. Lochnagar provides many pins which can generally be used for an audio function such as an AIF or a PDM interface, but also as GPIOs. Signed-off-by:
Charles Keepax <ckeepax@opensource.cirrus.com> Reviewed-by:
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Charles Keepax authored
Lochnagar is an evaluation and development board for Cirrus Logic Smart CODEC and Amp devices. It allows the connection of most Cirrus Logic devices on mini-cards, as well as allowing connection of various application processor systems to provide a full evaluation platform. This driver supports the board controller chip on the Lochnagar board. Signed-off-by:
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Maxime Ripard authored
Our pinctrl drivers are consisting of some common code, and big pin tables that are SoC-specific. This is fine in most cases, but when you want to reduce the size of the particular kernel image, those big tables are, well, quite big. We haven't had the option to disable them in the past since they were hidden Kconfig options based on the SoC support. However, that granularity isn't great since we don't have one Kconfig option per-SoC, but rather one by family. Make those options selectable by the user so that they can disable it if needed, while keeping the current default to not change the standard case. Acked-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by:
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Maxime Ripard authored
Our pin controller can configure the pins no matter how they are muxed, so it makes sense to allow this for GPIOs as well. Add the generic set_config function so that we can rely on the existing pinctrl code we have. Signed-off-by:
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Maxime Ripard authored
Lines are usually ended with a semi-column in C, yet this was copied from a structure declaration to the init variant while keeping the comma at the end. Make sure we have a normal syntax, instead of multiple assignments. Fixes: d83c82ce ("pinctrl: sunxi: support multiple pin controller") Signed-off-by:
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Maxime Ripard authored
The sunxi pinctrl only implements the pin_config_group_set callback at the moment, whereas the gpiochip_generic_config function relies on pin_config_set. Rework the functions a little to support pin_config_set, and rely on it for pin_config_group_set. Signed-off-by:
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- 02 Apr, 2019 20 commits
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Takeshi Kihara authored
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of Feb 12, 2019, the sel_ndfc MOD_SEL register bit is renamed to sel_ndf. Update the pin control drivers to reflect this. Signed-off-by:
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Takeshi Kihara authored
According to the R-Car Gen3 Hardware Manual Errata for Rev 0.80 of Dec 22, 2017, and the Errata for Rev 1.50 of Dec 25, 2018, MOD_SEL0 register bits 3, 4, 17, and 18 are renamed from SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}. Update the pin control drivers to reflect this. Signed-off-by: -
Takeshi Kihara authored
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of Feb 12, 2019, the RTS{0,1,3,4}_#/TANS pin names defined in the GPSR and IPSR registers are renamed to RTS{0,1,3,4}_#. This patch updates the pin control drivers to reflect this. Signed-off-by: -
Takeshi Kihara authored
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Jun 4, 2018, the CC5_OSCOUT pin is removed. Update the pin control drivers to reflect this. Signed-off-by:
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Takeshi Kihara authored
The HDMI CEC function is not supported by the R-Car Gen3 Hardware Manual Rev 1.00. Therefore, delete the corresponding pin groups and functions, and rename the HDMI[01]_CEC definitions to match their GPIO functionality. Signed-off-by:
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Takeshi Kihara authored
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, there is no need to configure MOD_SEL1 bit30 when the SSI_SCK2_{A,B} or SSI_WS2_{A,B} pin functions are selected. Signed-off-by: -
Takeshi Kihara authored
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, there is no need to configure MOD_SEL1 bit31 when the SIM0_D_{A,B} pin function is selected. Signed-off-by: -
Takeshi Kihara authored
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, the MOD_SEL0 bit16 must be set to 0 when the NFALE_A and NFRB_N_A pin functions are selected. Signed-off-by:
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Geert Uytterhoeven authored
- The IPSR field is meant for documentation only, - The function name refers to the pin function, not to the IPSR field. Signed-off-by:Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
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Geert Uytterhoeven authored
rza1_get_bit() is just a single register read. Hence there's no need to synchronize it with other register writes to the same bank. Signed-off-by:
Jacopo Mondi <jacopo@jmondi.org>
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Geert Uytterhoeven authored
Add a run-time check to the PINMUX_CFG_REG_VAR() macro, to ensure the number of provided enum IDs is correct. This cannot be done at build time, as the number of values depends on the variable-width fields in the config register. This helps catching bugs early. Signed-off-by: -
Geert Uytterhoeven authored
Add build-time checks to the PINMUX_CFG_REG() and PINMUX_DATA_REG() macros, to ensure the number of provided enum IDs is correct. This helps catching bugs early. Signed-off-by: -
Geert Uytterhoeven authored
Currently the PINMUX_DATA_REG() macro must be followed by initialization data, specifying all enum IDs. Hence the macro itself does not know anything about the enum IDs, preventing the macro from performing any validation on it. Make the macro accept the enum IDs as a parameter, and update all users. Note that array data enclosed by curly braces cannot be passed to a macro as a parameter, hence the enum IDs are wrapped using the GROUP() macro. No functional changes. Signed-off-by: -
Geert Uytterhoeven authored
Currently the PINMUX_CFG_REG_VAR() macro must be followed by initialization data, specifying all enum IDs. Hence the macro itself does not know anything about the enum IDs, preventing the macro from performing any validation on it. Make the macro accept the enum IDs as a parameter, and update all users. Note that array data enclosed by curly braces cannot be passed to a macro as a parameter, hence both the register field widths and the enum IDs are wrapped using the GROUP() macro. No functional changes. Signed-off-by: -
Geert Uytterhoeven authored
Currently the PINMUX_CFG_REG() macro must be followed by initialization data, specifying all enum IDs. Hence the macro itself does not know anything about the enum IDs, preventing the macro from performing any validation on it. Make the macro accept the enum IDs as a parameter, and update all users. Note that array data enclosed by curly braces cannot be passed to a macro as a parameter, hence the enum IDs are wrapped using a new macro GROUPS(). No functional changes. Signed-off-by: -
Geert Uytterhoeven authored
Enable compile-testing of all Renesas SuperH and ARM pin control drivers, in a similar way as was done before for clock and SoC drivers in commits 371dd373 ("clk: renesas: Allow compile-testing of all (sub)drivers") and 8be381a1 ("soc: renesas: Rework Kconfig and Makefile logic"). The SuperH pin control drivers need specific include files, hence make sure they are always found when compile-testing. Signed-off-by:
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Geert Uytterhoeven authored
When compile-testing on arm: arch/sh/include/cpu-sh4/cpu/sh7786.h: In function ‘sh7786_mm_sel’: arch/sh/include/cpu-sh4/cpu/sh7786.h:135:21: warning: passing argument 1 of ‘__raw_readl’ makes pointer from integer without a cast [-Wint-conversion] return __raw_readl(0xFC400020) & 0x7; ^~~~~~~~~~ In file included from include/linux/io.h:25:0, from arch/sh/include/cpu-sh4/cpu/sh7786.h:14, from drivers/pinctrl/sh-pfc/pfc-sh7786.c:15: arch/arm/include/asm/io.h:113:21: note: expected ‘const volatile void *’ but argument is of type ‘unsigned int’ #define __raw_readl __raw_readl ^ arch/arm/include/asm/io.h:114:19: note: in expansion of macro ‘__raw_readl’ static inline u32 __raw_readl(const volatile void __iomem *addr) ^~~~~~~~~~~ __raw_readl() on SuperH is a macro that casts the passed I/O address to the correct type, while the implementations on most other architectures expect to be passed the correct pointer type. Add an explicit cast to fix this. Note that this also gets rid of a sparse warning on SuperH: arch/sh/include/cpu-sh4/cpu/sh7786.h:135:16: warning: incorrect type in argument 1 (different base types) arch/sh/include/cpu-sh4/cpu/sh7786.h:135:16: expected void const volatile [noderef] <asn:2>*<noident> arch/sh/include/cpu-sh4/cpu/sh7786.h:135:16: got unsigned int Signed-off-by: -
Geert Uytterhoeven authored
Source files using -Exxx error codes should include <linux/errno.h>. On ARM, this header file is included indirectly; on SuperH, it is not, leading to "error: ‘EINVAL’ undeclared" failures when enabling compile-testing later. Signed-off-by:
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Geert Uytterhoeven authored
Pinctrl drivers for SuperH platforms use legacy function GPIOs. Currently this support is compiled in based on the SUPERH platform dependency, which hinders the introduction of compile-testing support for the affected pinctrl drivers. Introduce a new Kconfig symbol PINCTRL_SH_FUNC_GPIO, which is auto-selected when needed. This symbol in turn selects PINCTRL_SH_PFC_GPIO, to reduce the number of per-driver selects. Signed-off-by:
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Geert Uytterhoeven authored
Perform some basic sanity checks on all built-in pinmux tables when DEBUG is defined, to help catching bugs early. For now the following checks are included: - Check register and field widths in descriptors for config registers with variable-width fields, - Check relations between pin groups and functions: - All pin functions must refer to existing pin groups, - All pin groups must be referred to by a pin function, - Warn if a pin group is referred to by multiple pin functions (which is OK for backwards-compatibility aliases), - Provide suggestions for reducing table sizes: reserved fields of more than 3 bits can better be split in smaller subfields, as the storage need is proportional to the square of the width of the (sub)field, Note that a dummy non-matching entry is added to the DT match table for checking r8a7795es1_pinmux_info, as R-Car H3 ES1.0 is matched using soc_device_match() in r8a7795_pinmux_init(), instead of by the DT match table. Signed-off-by:
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- 24 Mar, 2019 1 commit
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Jan Kundrát authored
This function is needed in mcp23s08. That driver is a special snowflake because it supports several hardware chips as a single "GPIO chip" under Linux. Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
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- 18 Mar, 2019 2 commits
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Marek Vasut authored
The TDSELCTRL register is responsible for configuring the SDHI/MMC clock return path delay and may be adjusted by the bootloader. Retain the value across suspend/resume to prevent hardware instability after resume. Signed-off-by:
Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by:
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Fabrizio Castro authored
CANFD is found also on the R8A774C0, therefore move CANFD pin groups and functions to "common". Signed-off-by:
Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by:
Chris Paterson <chris.paterson2@renesas.com> Signed-off-by:
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