- 23 Mar, 2023 5 commits
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Kathiravan T authored
IPQ5332 APSS PLL is of type Stromer Plus. Add support for the same. To configure the stromer plus PLL separate API (clock_stromer_pll_configure) to be used. To achieve this, introduce the new member pll_type in device data structure and call the appropriate function based on this. Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230217083308.12017-4-quic_kathirav@quicinc.com
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Kathiravan T authored
Add IPQ5332 compatible to A53 PLL bindings. Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Kathiravan T authored
APSS PLL found on the IPQ8074 and IPQ6018 are of type Huayra PLL. But, IPQ5332 APSS PLL is of type Stromer Plus. To accommodate both these PLLs, refactor the driver to take the clk_alpha_pll, alpha_pll_config via driver data. Reviewed-by:
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Krzysztof Kozlowski authored
The qcom,sdx55-apcs-gcc is followed by another compatible (syscon), thus the 'if' clause must match by contains. Fixes: 0d17014e ("dt-bindings: mailbox: Add binding for SDX55 APCS") Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
Manivannan Sadhasivam <mani@kernel.org> Signed-off-by:
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Krzysztof Kozlowski authored
SDX55 and SDX65 DTS takes clocks in a bit different order. Adjust bindings to the DTS. Fixes: 0d17014e ("dt-bindings: mailbox: Add binding for SDX55 APCS") Signed-off-by:
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- 22 Mar, 2023 3 commits
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Konrad Dybcio authored
The USB controller on msm8998 doesn't retain its state when the system goes into low power state and the GDSCs are turned off. This can be observed by the USB connection not coming back alive after putting the device into suspend, essentially breaking USB. Work around this by updating the .pwrsts for the USB GDSCs so they only transition to retention state in low power. This change should be reverted when a proper suspend sequence is implemented in the USB drivers. Signed-off-by:
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Konrad Dybcio authored
The USB controller on MSM8996 doesn't retain its state when the system goes into low power state and the GDSCs are turned off. This can be observed by the USB connection not coming back alive after putting the device into suspend, essentially breaking USB. Work around this by updating the .pwrsts for the USB GDSCs so they only transition to retention state in low power. This change should be reverted when a proper suspend sequence is implemented in the USB drivers. Signed-off-by:
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Konrad Dybcio authored
The USB controller on sm6375 doesn't retain its state when the system goes into low power state and the GDSCs are turned off. This can be observed by the USB connection not coming back alive after putting the device into suspend, essentially breaking USB. Work around this by updating the .pwrsts for the USB GDSCs so they only transition to retention state in low power. This change should be reverted when a proper suspend sequence is implemented in the USB drivers. Signed-off-by:
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- 16 Mar, 2023 5 commits
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Otto Pflüger authored
MSM8917 has mostly the same rpm clocks as MSM8953, but lacks RF_CLK3 and IPA_CLK and additionally has the BIMC_GPU clock. Signed-off-by:
Otto Pflüger <otto.pflueger@abscue.de> Reviewed-by:
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Otto Pflüger authored
This driver provides clocks, resets and power domains needed for various components of the MSM8917 SoC and the very similar QM215 SoC. According to [1] in the downstream kernel, the GPU clock has a different source mapping on QM215 (gcc_gfx3d_map vs gcc_gfx3d_map_qm215). [1]: https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LF.UM.8.6.2-28000-89xx.0/include/dt-bindings/clock/msm-clocks-hwio-8952.h#L298Signed-off-by:
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Bjorn Andersson authored
Merge MSM8917 Global Clock Controller and RPM clock controller bindings through topic branch, to make it possible to introduce in Devicetree source depending on these.
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Otto Pflüger authored
Document the qcom,rpmcc-msm8917 compatible. Signed-off-by:
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Otto Pflüger authored
Add a device tree binding to describe clocks, resets and power domains provided by the global clock controller on MSM8917 SoCs and the very similar QM215 SoCs. Add the new compatibles to qcom,gcc-msm8909.yaml. There is no need to create another YAML file because the bindings are identical (MSM8917 GCC requires the same parent clocks as the MSM8909 GCC). Signed-off-by:
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- 15 Mar, 2023 11 commits
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Rayyan Ansari authored
Add the XO and XO_A clocks to the MSM8974 clock list, which is also used on MSM8226. Signed-off-by:
Rayyan Ansari <rayyan@ansari.sh> Tested-by:
Luca Weiss <luca@z3ntu.xyz> Reviewed-by:
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Christian Marangi authored
Rework kpss-gcc driver Documentation to yaml Documentation and move it to clock as it's a clock-controller. The current kpss-gcc Documentation have major problems and can't be converted directly. Introduce various changes to the original Documentation. Add #clock-cells additional binding as this clock outputs a static clk named acpu_l2_aux with supported compatible. Only some compatible require and outputs a clock, for the others, set only the reg as a required binding to correctly export the kpss-gcc registers. As the reg is shared also add the required syscon compatible. Signed-off-by:
Christian Marangi <ansuelsmth@gmail.com> Reviewed-by:
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Christian Marangi authored
Convert kpss-acc driver Documentation to yaml. The original Documentation was wrong all along. Fix it while we are converting it. The example was wrong as kpss-acc-v2 should only expose the regs but we don't have any driver that expose additional clocks. The kpss-acc driver is only specific to v1. For this exact reason, split the Documentation to 2 different schema, v1 as clock-controller and v2 for power-manager as per msm-3.10 specification, the exposed regs handle power manager. Signed-off-by:
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Kathiravan T authored
Clock framework disables the GPLL4 source since there are no active users for this source currently. Some of the clocks initialized by the bootloaders uses the GPLL4 as the source. Due to this, when the GPLL4 is disabled by the clock framework, system is going for the reboot. To avoid this, mark the GPLL4 as ignore unused so that clock framework doesn't disable it. Once the users of this source is enabled, we can get rid of this flag. Signed-off-by:
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Kathiravan T authored
Add support for the global clock controller found on IPQ5332 SoC. PLL used on IPQ5332 is of type Stromer Plus PLL, however the programming sequence is same as Stromer PLL, so lets re-use the Stromer PLL ops. Signed-off-by:
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Kathiravan T authored
Add the support for stromer plus pll, which is found on the IPQ5332 SoCs. Programming sequence is same as the stromer pll, so we can re-use the same. Reviewed-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
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Varadarajan Narayanan authored
Add programming sequence support for managing the Stromer PLLs. Reviewed-by:
Sricharan R <quic_srichara@quicinc.com> Signed-off-by:
Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by:
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Bjorn Andersson authored
Merge the IPQ5332 Global Clock Controller binding through a topic branch to make it possible to include in Devicetree source as well.
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Kathiravan T authored
Add binding for the Qualcomm IPQ5332 Global Clock Controller. Reviewed-by:
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Tom Rix authored
gcc with W=1 reports these errors drivers/clk/qcom/gpucc-sm6375.c:145:37: error: ‘gpucc_parent_data_2’ defined but not used [-Werror=unused-const-variable=] 145 | static const struct clk_parent_data gpucc_parent_data_2[] = { | ^~~~~~~~~~~~~~~~~~~ drivers/clk/qcom/gpucc-sm6375.c:139:32: error: ‘gpucc_parent_map_2’ defined but not used [-Werror=unused-const-variable=] 139 | static const struct parent_map gpucc_parent_map_2[] = { | ^~~~~~~~~~~~~~~~~~ These variables are not used, so remove them. Signed-off-by:Tom Rix <trix@redhat.com> Reviewed-by:
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Konrad Dybcio authored
Add the PARENT_ENABLE flag to prevent the clock from getting stuck at boot and use floor_ops to avoid SDHCI overclocking. Fixes: 496d1a13 ("clk: qcom: Add Global Clock Controller driver for QCM2290") Signed-off-by:
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- 14 Mar, 2023 5 commits
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Robert Marko authored
Convert the IPQ4019 GCC driver to use parent data instead of global name matching. Utilize ARRAY_SIZE for num_parents instead of hardcoding the value. Signed-off-by:
Robert Marko <robert.marko@sartura.hr> Signed-off-by:
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Robert Marko authored
Move pcnoc clocks up just after PLL-s to be able to use their HW fields. Signed-off-by:
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Robert Marko authored
Move PLL clock declarations up, before clock parent tables, so that we can use pll hw clock fields in the next commit. Signed-off-by:
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Robert Marko authored
Start off IPQ4019 GCC conversion by converting XO and sleep clks to parent data in order to directly pass them. Signed-off-by:
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Robert Marko authored
Move schema for the GCC on IPQ4019 platform to a separate file to be able to allow passing XO and sleep clks directly to GCC. Signed-off-by:
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- 13 Mar, 2023 11 commits
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Danila Tikhonov authored
Add support for the global clock controller found on SM7150 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Co-developed-by:
David Wronek <davidwronek@gmail.com> Signed-off-by:
Danila Tikhonov <danila@jiaxyga.com> Reviewed-by:
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Bjorn Andersson authored
Merge SM7180 Global Clock Controller binding through a dedicated topic branch, so that it can be introduced into the Devicetree source tree as well in the same kernel release.
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Danila Tikhonov authored
Add device tree bindings for global clock subsystem clock controller for Qualcomm Technology Inc's SM7150 SoCs. Co-developed-by:
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Luca Weiss authored
.determine_rate is meant to replace .round_rate. The former comes with a benefit which is especially relevant on 32-bit systems: since .determine_rate uses an "unsigned long" (compared to a "signed long" which is used by .round_rate) the maximum value on 32-bit systems increases from 2^31 (or approx. 2.14GHz) to 2^32 (or approx. 4.29GHz). Signed-off-by:
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Luca Weiss authored
.determine_rate is meant to replace .round_rate. The former comes with a benefit which is especially relevant on 32-bit systems: since .determine_rate uses an "unsigned long" (compared to a "signed long" which is used by .round_rate) the maximum value on 32-bit systems increases from 2^31 (or approx. 2.14GHz) to 2^32 (or approx. 4.29GHz). Signed-off-by:
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Konrad Dybcio authored
Add support for the GPU clock controller found on SM6115. Signed-off-by:
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Konrad Dybcio authored
Add support for the GPU clock controller found on SM6375. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Konrad Dybcio authored
Add support for the GPU clock controller found on SM6125. Reviewed-by:
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Konrad Dybcio authored
Prefix the "branch enable" registers with CBCR_ to be closer to what they are actually called in Qualcomm terms, use GENMASK instead of shifting values around and adjust their usage accordingly. Signed-off-by:
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Konrad Dybcio authored
Move the definitions of CBCR bits to the branch header file. Signed-off-by:
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Konrad Dybcio authored
HLOS-controlled branch clocks on non-ancient Qualcomm platforms feature SLEEP and WAKE fields which can be written to to configure how long the clock hardware should wait internally before being (un)gated. Some very sensitive clocks need to have these values programmed to prevent putting the hardware in a not-exactly-good state. Add definitions of these fields and introduce helpers for setting them inside clock drivers. Reviewed-by:
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