- 06 Dec, 2023 38 commits
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Alex Hung authored
[WHAT] Handle writeback requests and fill in the required information for DWB programming and setup. Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Harry Wentland authored
[WHAT] Writeback connectors don't have a physical sink but DC still needs a sink to function. Create a fake sink and stream for writeback connectors Tested-by:
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Harry Wentland authored
[WHY] We need to track the dc_link and it would get confusing if re-using the amdgpu_dm_connector. [HOW] Creating new amdgpu_dm_wb_connector. Tested-by:
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Alex Hung authored
[WHY & HOW] This is to check connector type to avoid unhandled null pointer for writeback connectors. Tested-by:
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Harry Wentland authored
[WHAT] We need to use this function for both amdgpu_dm_connectors and drm_writeback_connectors. Modify it to operate on a drm_connector as a common base. Tested-by:
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Harry Wentland authored
[WHY] We will be dealing with two types of connector: amdgpu_dm_connector and drm_writeback_connector. [HOW] We want to find both and then cast to the appriopriate type afterwards. Tested-by:
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Harry Wentland authored
[WHY] Writeback connectors are based on a different object: drm_writeback_connector, and are therefore different from amdgpu_dm_connector. We need to be careful to ensure code designed for amdgpu_dm_connector doesn't inadvertently try to operate on a drm_writeback_connector. [HOW] Skip them when connector type is DRM_MODE_CONNECTOR_WRITEBACK. Tested-by:
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Alex Hung authored
[WHAT] Create a drm_writeback_connector when connector signal equals SIGNAL_TYPE_VIRTUAL. Tested-by:
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Harry Wentland authored
[WHAT] Prepare a virtual connector for writeback. Tested-by:
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Harry Wentland authored
[WHY] Previously this only excluded build for a few amdgpu_dm binaries which makes no sense. [HOW] Wrap the entire Makefile in "ifneq ($(CONFIG_DRM_AMD_DC),)" Tested-by:
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Alex Hung authored
Virtual stream encoder should not be a free match for thunderbolt or usbc, and thus should be avoided. Tested-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by:
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Wenjing Liu authored
Current implementation will choose to use refclk as dscclk. This is not recommended by hardware team as refclk is a fixed value which could cause unnecessary power consumption or it could be not enough for large DSC timings. So we are adding new interfaces so we could switch to use dynamically generated DSCCLK by DTO. So DSCCLK is programmable based on current pixel clock and dispclk. Tested-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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Dennis Chan authored
In previous case, Replay didn't identify the IRQ type, This commit fixes the issues for the interrupt. Tested-by:
Robin Chen <robin.chen@amd.com> Acked-by:
Dennis Chan <dennis.chan@amd.com> Signed-off-by:
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Dillon Varone authored
Add function to handle deep copying dml2 context. Tested-by:
Dillon Varone <dillon.varone@amd.com> Signed-off-by:
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Yihan Zhu authored
Missing clock gating programming blocks memory power on from boot up. Tested-by:
Chris Park <chris.park@amd.com> Acked-by:
Yihan Zhu <yihan.zhu@amd.com> Signed-off-by:
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Ivan Lipski authored
[WHY] Some eDP panels's ext caps don't write initial value cause the value of dpcd_addr(0x317) is random. It means that sometimes the eDP will clarify it is OLED, miniLED...etc cause the backlight control interface is incorrect. [HOW] Add a new panel patch to remove sink ext caps(HDR,OLED...etc) Tested-by:
Sun peng Li <sunpeng.li@amd.com> Acked-by:
Ivan Lipski <ivlipski@amd.com> Signed-off-by:
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Nicholas Susanto authored
[Why] When switching to another HDMI mode, we are unnecesarilly disabling/enabling FIFO causing both HPO and DIG registers to be set at the same time when only HPO is supposed to be set. This can lead to a system hang the next time we change refresh rates as there are cases when we don't disable OTG/FIFO but FIFO is enabled when it isn't supposed to be. [How] Removing the enable/disable FIFO entirely. Tested-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Nicholas Susanto <nicholas.susanto@amd.com> Signed-off-by:
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Charlene Liu authored
This is w/a: we need to keep domain 24 power up in driver side, and let dmubfw handle it for S0i3. For last display unplugged, if OTG in PG, no interrupt call back coming. Tested-by:
Charlene Liu <charlene.liu@amd.com> Signed-off-by:
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Relja Vojvodic authored
HW registers were being read to quickly, causing incorrect values to be logged after a clock frequency was changed Tested-by:
Martin Leung <martin.leung@amd.com> Acked-by:
Relja Vojvodic <relja.vojvodic@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] The DC debug options currently do not function for dynamically adjusting our watermarks. [How] Hook them up before passing them to DML2. Also make sure we're using dc->bb_overrides since dc->debug isn't populated during dc_construct. Tested-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
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Charlene Liu authored
w/a use case: - dual display, compliance, toggling between the displays - switching between 120Hz 420 -> 144Hz 444 and vice versa - switching between 144Hz -> 60Hz TMDS or vice versa It'd typically involve TMDS in some capacity since that's the only link signal we leave the OTG running but DIO/PHY off you can hit this in cases where you have multiple displays as well it syncs with the first active OTG, so if you had OTG[0] mapped and FIFO off you'd hit it even if OTG[1] was mapped and had FIFO Tested-by:
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Chris Park authored
[Why] BIOS FW info version 3.5 is introduced to support new ASICs, but it's content is currently same as 3.4. [How] Include minor version 5 in parsing to enable support. Tested-by:
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George Shen authored
[Why] The is_automated flag logic only applies to USB4 DPIA links during DP LL compliance test automation. The flag should not be set for non-DPIA cases. [How] Add check for DPIA link endpoint type before setting the flag. Also, rename is_automated to skip_fallback_on_link_loss for clarity. Tested-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Reviewed-by:
George Shen <george.shen@amd.com> Signed-off-by:
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Johnson Chen authored
Add guard for NULL pointer access Tested-by:
Johnson Chen <johnson.chen@amd.com> Signed-off-by:
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Alvin Lee authored
VBIOS has suggested to use channel_width=2 for any ASIC that uses vram info 3.0. This is because channel_width in the vram table no longer represents the memory width Tested-by:
Samson Tam <samson.tam@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
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Ilya Bakoulin authored
Changing PBN calculation to be more in line with spec. We don't need to inflate PBN_NATIVE value by the 1.006 margin, since that is already taken care of in the get_pbn_per_slot function. Tested-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Signed-off-by:
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Charlene Liu authored
Rollback to new context for active display: this was previous tested sequence. Avoid to do OTG master toggle is no active display at all, this w/a was for fifo err. Tested-by:
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Josip Pavic authored
[Why] Larger data blocks are expected to be transferred between driver and FW in the future. [How] Embiggen the scratch buffer to a cromulent size. Tested-by:
Josip Pavic <josip.pavic@amd.com> Signed-off-by:
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Krunoslav Kovac authored
We use spatial dither by default for all output bpc (6/8/10). While it makes some sense for FP16, for ARGB2101010 surfaces it makes little sense as even if we skip color pipeline to preserve bit accuracy, spatial dither adds random noise so a few percent pixels are 1 bit off. This commit chages the 10bpc out dither policy to rounding. Also, in Polaris/Vega times, policy used to be round for 10bpc out; it looks like it got inadvertently changed for Navi. Difference is only detectable with capture cards. Tested-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Acked-by:
Krunoslav Kovac <krunoslav.kovac@amd.com> Signed-off-by:
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Lewis Huang authored
[Why] OTG inst and pwrseq inst mapping is not align therefore we cannot use otg_inst as pwrseq inst to get DCIO register. [How] 1. Pass the correct pwrseq instance to dmub when set abm pipe. 2. LVTMA control index change from panel_inst to pwrseq_inst. Tested-by:
Phil Hsieh <phil.hsieh@amd.com> Acked-by:
Lewis Huang <lewis.huang@amd.com> Signed-off-by:
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Daniel Miess authored
[Why] Some registers needed for root clock gating in dcn35 are not defined in the dccg header. [How] Add the needed registers and temporarily disable some register writes that are now taking place successfully until the registers can be properly enabled. Tested-by:
Daniel Miess <daniel.miess@amd.com> Signed-off-by:
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Xiaogang Chen authored
This patch implements partial migration/mapping for gpu/cpu page faults in SVM according to migration granularity(default 2MB). A svm range may include pages from both system ram and vram of one gpu now. These chagnes are expected to improve migration performance and reduce mmu callback and TLB flush workloads. Signed-off-by:
Xiaogang Chen <xiaogang.chen@amd.com> Reviewed-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
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Michael Strauss authored
[WHY] Many DCN generations only have two HPO link encoders and therefore only support driving a max of two DP2 PHYs. DP2 MST hubs currently can not pass 3x display validation as each downstream sink is enumerated as separate DP2 output. [HOW] Count MST hubs once by treating only 1st remote sink in topology as an encoder. Tested-by:
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Relja Vojvodic authored
[why] When querying DML for a vlevel after pipes have been split or merged the ODM policy would revert to a default policy, which could cause the query to use the incorrect ODM status. In this case ODM 2to1 was validated, but the last DML query would assume no ODM and return the incorrect vlevel. [how] Added ODM check to apply the correct ODM policy before querying DML. Tested-by:
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Charlene Liu authored
Fix issue when override level bigger than default. Levels 5, 6, and 7 had zero stutter latency, this is because override level being initialized after stutter latency inits. Tested-by:
Syed Hassan <syed.hassan@amd.com> Reviewed-by:
Allen Pan <allen.pan@amd.com> Acked-by:
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Alvin Lee authored
Optimize fast validation cases to only validate the highest voltage level. This works because during fast validation we only care if the mode can be supported or not (at any vlevel). Tested-by:
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Bokun Zhang authored
- Move VCN4's fw_shared initialization to a separated function. This way, the function can be reused at different locations. Signed-off-by:
Bokun Zhang <bokun.zhang@amd.com> Reviewed-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
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Jiadong Zhu authored
Disable MCBP(mid command buffer preemption) by default as old Mesa hangs with it. We shall not enable the feature that breaks old usermode driver. Fixes: 50a7c876 ("drm/amdgpu: enable mcbp by default on gfx9") Signed-off-by:
Jiadong Zhu <Jiadong.Zhu@amd.com> Acked-by:
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- 05 Dec, 2023 1 commit
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https://gitlab.freedesktop.org/agd5f/linuxDave Airlie authored
amd-drm-next-6.8-2023-12-01: amdgpu: - Add new 64 bit sequence number infrastructure. This will ultimately be used for user queue synchronization. - GPUVM updates - Misc code cleanups - RAS updates - DCN 3.5 updates - Rework PCIe link speed handling - Document GPU reset types - DMUB fixes - eDP fixes - NBIO 7.9 updates - NBIO 7.11 updates - SubVP updates - DCN 3.1.4 fixes - ABM fixes - AGP aperture fix - DCN 3.1.5 fix - Fix some potential error path memory leaks - Enable PCIe PMEs - Add XGMI, PCIe state dumping for aqua vanjaram - GFX11 golden register updates - Misc display fixes amdkfd: - Migrate TLB flushing logic to amdgpu - Trap handler fixes - Fix restore workers handling on suspend and reset - Fix possible memory leak in pqm_uninit() radeon: - Fix some possible overflows in command buffer checking - Check for errors in ring_lock From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231201181743.5313-1-alexander.deucher@amd.comSigned-off-by:
Dave Airlie <airlied@redhat.com>
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- 30 Nov, 2023 1 commit
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Mario Limonciello authored
During hibernate sequence the source context might not have a clk_mgr. So don't use it to look for DML2 support. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2980 Fixes: 7966f319 ("drm/amd/display: Introduce DML2") Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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