- 26 Oct, 2020 35 commits
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Dmytro Laktyushkin authored
Prevent null pointer access when checking odm tree. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: <stable@vger.kernel.org>
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Rodrigo Siqueira authored
The clock state update is the source of many problems, and capturing this sort of information helps debug. This commit introduces tracepoints for capturing clock values and also add traces in DCE, DCN1, DCN2x, and DCN3. Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
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Rodrigo Siqueira authored
This commit introduces a trace mechanism for struct pipe_ctx by adding a middle layer struct in the amdgpu_dm_trace.h for capturing the most important data from struct pipe_ctx and showing its data via tracepoint. This tracepoint was added to dc.c and dcn10_hw_sequencer, however, it can be added to other DCN architecture. Signed-off-by:
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Rodrigo Siqueira authored
Debug amdgpu_dm could be a complicated task, therefore, this commit adds tracepoints in some convenient functions such as plane and connector check inside amdgpu_dm. Signed-off-by:
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Rodrigo Siqueira authored
amdgpu_dc_rreg and amdgpu_dc_wreg are very similar, for this reason, this commits abstract these two events by using DECLARE_EVENT_CLASS and create an instance of it for each one of these events. Signed-off-by:
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Rodrigo Siqueira authored
Our DC currently uses some of the tracepoint function inside a DC header, which means that many other files implicitly include part of the trace function. This situation limits how we can expand this feature for other parts of the driver by generating multiple compilation errors when we try to reuse some of the existing structures. This commit decouples part of the amdgpu_dm_trace from DC core to simplify the trace enlargement in future changes. Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Anthony Koo authored
| [Header Changes] | - Add new SCRATCH15 boot option and fw_state member to skip | phy access | - Add new SCRATCH15 boot option and fw_state member to disable | clk gating | - Add defines for AUX return status | - Add defines for HPD events Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Martin Leung authored
why: oem-related ddc read/write fails without these regs how: copy from hw_factory_dcn20.c Signed-off-by:
Martin Leung <martin.leung@amd.com> Acked-by:
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Felipe Clark authored
[WHY] It was detected in some Freesync HDR tests that displays were not reaching their maximum nominal brightness. [HOW] The Multi-plane combiner (MPC) Output Gamma (OGAM) block builds a discrete Lookup Table (LUT). When the display's maximum brightness falls in between two values, having to be linearly interpolated by the hardware, rounding issues might occur that will cause the display to never reach its maximum brightness. The fix involves doing the calculations backwards, ensuring that the interpolation in the maximum brightness values translates to an output of 1.0. Signed-off-by:
Felipe Clark <felclark@amd.com> Acked-by:
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Aric Cyr authored
[Why] When ODM combine is in use we trigger multiple update events causing issues with variable refresh rate. [How] Only trigger on a single ODM instance. Signed-off-by:
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Alvin Lee authored
[Why] We should leave GSL if we're not doing immediate flip no matter if we're doing pipe split or not [How] Check for updating GSL state whenever we're not doing immediate flip v2: Squash in build fix (Alex) Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
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Yu-Ting Shen authored
[WHY] VBIOS will not enable VSC_SDP during pre-OS to lead MISC1[6] wasn't matched with driver. [HOW] disabled seamless boot if sink supports VSC_SDP Signed-off-by:
Yu-Ting Shen <Yu-ting.Shen@amd.com> Acked-by:
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Yongqiang Sun authored
[Why] right side visual confirm is too thick due to it is 4 times of left side (16 lines). [How] Change factor from 4 to 2. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Isabel Zhang authored
[Why] Causes underflow regression [How] This reverts commit 99d1437aSigned-off-by:
Isabel Zhang <isabel.zhang@amd.com> Acked-by:
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Brandon Syu authored
[Why] For some monitors, they can't display under BIOS with avmute enabled. [How] Add monitor patch for skip avmute action. Signed-off-by:
Brandon Syu <Brandon.Syu@amd.com> Acked-by:
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Roman Li authored
[Why] All DCN3x resources share ABM_MASK_SH_LIST_DCN301 definition. The naming is misleading since it looks like DCN30 code depends on next version DCN301, which in fact is vice-versa. [How] Refactor the naming to ABM_MASK_SH_LIST_DCN30. v2: squash in build fixes (Alex) Signed-off-by:
Roman Li <roman.li@amd.com> Acked-by:
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Martin Leung authored
why: missing OEM data to control graphics card functions how: load it into init_data. copied over from dcn2 implementation. copied destruction sequence as well. Signed-off-by:
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Sung Lee authored
[WHY & HOW] Currently disable 48mhz debug option only disables on boot. Need to put option check in update_clocks as well to make it affect more areas. Signed-off-by:
Sung Lee <sung.lee@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
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Nikola Cornij authored
[Why] Can be used for debug purposes [How] Add max target bpp override field and related handling Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Acked-by:
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Anthony Koo authored
| [Header Changes] | - Add GPINT to change timestamping mode for traces Signed-off-by:
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Reza Amini authored
[why] So we can track VSC SDP errors from display [how] Define the bit, and use it in driver logic Signed-off-by:
Reza Amini <Reza.Amini@amd.com> Acked-by:
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Taimur Hassan authored
[Why] Underflow counter increases in AGM when performing some mode switches due to timing sync, which is a known hardware issue. [How] Temporarily raise DPG height during timing sync so that underflow is not reported. Signed-off-by:
Taimur Hassan <syed.hassan@amd.com> Acked-by:
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Alvin Lee authored
[Why] If full pstate is not supported, we should set WM set A to 0 to prevent any hangs [How] If pstate is not supported, set watermark set A to 0 Signed-off-by:
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Eryk Brol authored
This reverts commit c44a22b3. Reason for revert: Patch introduces performance issues and might cause memory consistency problems with multiple connectors. Signed-off-by:
Eryk Brol <eryk.brol@amd.com> Acked-by:
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Ashley Thomas authored
[Why] Some sink devices wish to have access to the minimum HBlank supported by the ASIC. [How] Make the ASIC minimum HBlank available in Source Device information address 0x340. Signed-off-by:
Ashley Thomas <Ashley.Thomas2@amd.com> Acked-by:
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Dmytro Laktyushkin authored
[WHY & HOW] Enable ODM Combine + Fullscreen MPO on DCN2.1 For lower power consumption in video use cases. Signed-off-by:
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Dmytro Laktyushkin authored
[Why&How] Create a separate dcn21_fast_validate_bw function for dcn21. Signed-off-by:
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Sung Lee authored
[WHY] DF PState and Voltage State are coupled such that one cannot be raised without raising the other. This uses more power than is necessary in high bandwidth scenarios. [HOW] Add logic to create a new bounding box state that allows for DF PState to be low while Voltage State is high. Watermarks vlevel calculation logic was also udpated to assume state 1 contains the new optimized state. Signed-off-by:
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Christian König authored
Merge the functionality mostly into amdgpu_vm_bo_update_mapping. This way we can even handle small contiguous system pages without to much extra CPU overhead. v2: fix typo, keep the cursor as it is for now Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by: Madhav Chauhan <madhav.chauhan@amd.com> (v1) Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Christian König authored
Ideally this should be a multiple of the VM block size. 2MB should at least fit for Vega/Navi. Signed-off-by:
Madhav Chauhan <madhav.chauhan@amd.com> Reviewed-by:
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Tao Zhou authored
Per PMFW 59.9.0. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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John Clements authored
loaded fw can be queried from sys fs interface Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Xiaomeng Hou authored
enable IP discovery for vangogh. Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
Xiaomeng Hou <Xiaomeng.Hou@amd.com> Signed-off-by:
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- 23 Oct, 2020 5 commits
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David Galiffi authored
[why] get_pixel_clk_frequency_100hz is undefined in clock_source_funcs. [how] set function pointer: ".get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz" Signed-off-by:
David Galiffi <David.Galiffi@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
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xinhui pan authored
Size is page count here. Reviewed-by:
xinhui pan <xinhui.pan@amd.com> Signed-off-by:
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Mauro Carvalho Chehab authored
dm_comressor_info -> dm_compressor_info The kernel-doc markup is right, but the struct itself and their references contain a typo. Signed-off-by:
Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by:
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Mauro Carvalho Chehab authored
Some functions have different names between their prototypes and the kernel-doc markup. Acked-by:
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Mauro Carvalho Chehab authored
A kernel-doc markup can't be mixed with a random comment, as it causes parsing problems. While here, change an invalid kernel-doc markup into a common comment. Acked-by:
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