- 10 Apr, 2023 1 commit
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Tom Rix authored
smatch reports drivers/clk/mediatek/clk-fhctl.c:17:27: warning: symbol 'fhctl_offset_v1' was not declared. Should it be static? drivers/clk/mediatek/clk-fhctl.c:30:27: warning: symbol 'fhctl_offset_v2' was not declared. Should it be static? These variables are only used in one file so should be static. Signed-off-by:
Tom Rix <trix@redhat.com> Link: https://lore.kernel.org/r/20230406010935.1944976-1-trix@redhat.com Fixes: 8da312d6 ("clk: mediatek: fhctl: Add support for older fhctl register layout") Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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- 04 Apr, 2023 1 commit
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Stephen Boyd authored
This is copy/pasta that breaks modular builds. Fix the match table to use the right pointer, or the right device table type. And while we're including the header, fix the order to be linux, dt-bindings, and finally local. Cc: Garmin.Chang <Garmin.Chang@mediatek.com> Cc: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Fixes: f42b9e9a ("clk: mediatek: Add MT8188 wpesys clock support") Fixes: 0d2f2cef ("clk: mediatek: Add MT8188 adsp clock support") Fixes: e4aaa60e ("clk: mediatek: Add MT8188 vdosys0 clock support") Fixes: cfa4609f ("clk: mediatek: Add MT8188 vdosys1 clock support") Fixes: bb87c110 ("clk: mediatek: Add MT8188 vencsys clock support") Reported-by:
kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/oe-kbuild-all/202304011039.UBDX1UOT-lkp@intel.com/ Link: https://lore.kernel.org/oe-kbuild-all/202304020649.QO2HlpD5-lkp@intel.com/ Link: https://lore.kernel.org/oe-kbuild-all/202304021055.WDhQPcoS-lkp@intel.com/Signed-off-by:
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- 31 Mar, 2023 19 commits
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Garmin.Chang authored
Add MT8188 adsp clock controller which provides clock gate control for Audio DSP. Signed-off-by:
Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by:
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Garmin.Chang authored
Add MT8188 imp i2c wrapper clock controllers which provide clock gate control in I2C IP blocks. Signed-off-by:
Chen-Yu Tsai <wenst@chromium.org> Reviewed-by:
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Garmin.Chang authored
Add MT8188 wpesys clock controllers which provide clock gate control in Wrapping Engine. Signed-off-by:
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Garmin.Chang authored
Add MT8188 vppsys1 clock controller which provides clock gate controller for Video Processor Pipe. Signed-off-by:
Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by:
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Garmin.Chang authored
Add MT8188 vppsys0 clock controller which provides clock gate controller for Video Processor Pipe. Signed-off-by:
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Garmin.Chang authored
Add MT8188 vencsys clock controllers which provide clock gate control for video encoder. Signed-off-by:
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Garmin.Chang authored
Add MT8188 vdosys1 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by:
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Garmin.Chang authored
Add MT8188 vdosys0 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by:
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Garmin.Chang authored
Add MT8188 vdec clock controllers which provide clock gate control for video decoder. Signed-off-by:
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Garmin.Chang authored
Add MT8188 mfg clock controller which provides clock gate control for GPU. Signed-off-by:
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Garmin.Chang authored
Add MT8188 ipesys clock controller which provides clock gate control for Image Process Engine. Signed-off-by:
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Garmin.Chang authored
Add MT8188 imgsys clock controllers which provide clock gate control for image IP blocks. Signed-off-by:
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Garmin.Chang authored
Add MT8188 ccusys clock controller which provides clock gate control in Camera Computing Unit. Signed-off-by:
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Garmin.Chang authored
Add MT8188 camsys clock controllers which provide clock gate control for camera IP blocks. Signed-off-by:
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Garmin.Chang authored
Add MT8188 infrastructure clock controller which provides clock gate control for basic IP like pwm, uart, spi and so on. Signed-off-by:
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Garmin.Chang authored
Add MT8188 peripheral clock controller which provides clock gate control for ethernet/flashif/pcie/ssusb. Signed-off-by:
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Garmin.Chang authored
Add MT8188 topckgen clock controller which provides muxes, dividers to handle variety clock selection in other IP blocks. Signed-off-by:
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Garmin.Chang authored
Add MT8188 apmixedsys clock controller which provides Plls generated from SoC 26m and ssusb clock gate control. Signed-off-by:
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Garmin.Chang authored
Add the new binding documentation for system clock and functional clock on MediaTek MT8188. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230331123621.16167-2-Garmin.Chang@mediatek.comSigned-off-by:
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- 20 Mar, 2023 1 commit
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Arnd Bergmann authored
Just like in commit eddc6309 ("clk: mediatek: Ensure fhctl code is available for COMMON_CLK_MT6795"), these three need the shared driver code, otherwise they run into link errors such as: aarch64-linux/bin/aarch64-linux-ld: drivers/clk/mediatek/clk-mt8192-apmixedsys.o: in function `clk_mt8192_apmixed_probe': clk-mt8192-apmixedsys.c:(.text+0x134): undefined reference to `fhctl_parse_dt' Fixes: 45a5cbe0 ("clk: mediatek: mt8173: Add support for frequency hopping through FHCTL") Fixes: 4d586e10 ("clk: mediatek: mt8192: Add support for frequency hopping through FHCTL") Fixes: da4a82dc ("clk: mediatek: mt8195: Add support for frequency hopping through FHCTL") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20230320091353.1918439-1-arnd@kernel.orgReviewed-by:
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- 17 Mar, 2023 1 commit
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Stephen Boyd authored
Without this select we get linker errors when linking clk-mt6795-apmixedsys arm-linux-gnueabi-ld: drivers/clk/mediatek/clk-mt6795-apmixedsys.o: in function `clk_mt6795_apmixed_remove': clk-mt6795-apmixedsys.c:(.text+0x34): undefined reference to `mtk_clk_unregister_pllfhs' arm-linux-gnueabi-ld: drivers/clk/mediatek/clk-mt6795-apmixedsys.o: in function `clk_mt6795_apmixed_probe': clk-mt6795-apmixedsys.c:(.text+0x98): undefined reference to `fhctl_parse_dt' arm-linux-gnueabi-ld: clk-mt6795-apmixedsys.c:(.text+0xb8): undefined reference to `mtk_clk_register_pllfhs' arm-linux-gnueabi-ld: clk-mt6795-apmixedsys.c:(.text+0x1c4): undefined reference to `mtk_clk_unregister_pllfhs' Fixes: f222a1ba ("clk: mediatek: mt6795: Add support for frequency hopping through FHCTL") Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Cc: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by:
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- 13 Mar, 2023 17 commits
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AngeloGioacchino Del Regno authored
Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism; special note goes to the introduction of dummy clocks with ID 0 (where 0 is the first entry of a clock array) for each clock controller: this was necessary because of a mistake in the bindings for all MT8135 clock controllers, where the first clock has ID 1 (hence, array would start from element 1) instead of zero. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. While at it, also remove the __initconst annotation from all of the clock arrays as they are not only used during init anymore, but also during runtime. Signed-off-by:
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AngeloGioacchino Del Regno authored
In preparation for converting this driver to the common simple probe mechanism, join the root_clk_alias and top_divs mtk_fixed_factor arrays. This commit brings no functional change. Signed-off-by:
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AngeloGioacchino Del Regno authored
Convert apmixedsys clocks to be a platform driver; while at it, also add necessary error handling to the probe function, add a remove callback and provide a MODULE_DESCRIPTION(). This driver is now compatible with an eventual module build. Signed-off-by:
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AngeloGioacchino Del Regno authored
Instead of calling clk_prepare_enable() for clocks that shall stay enabled, use the CLK_IS_CRITICAL flag, which purpose is exactly that. Fixes: a8aede79 ("clk: mediatek: Add basic clocks for Mediatek MT8135.") Signed-off-by:
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AngeloGioacchino Del Regno authored
In preparation for migrating mt8135 clocks to the common simple probe mechanism, move the apmixedsys clocks to a different file. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add a MODULE_DEVICE_TABLE() on all clocks that can be built as modules to allow auto-load at boot. Signed-off-by:
Miles Chen <miles.chen@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks Link: https://lore.kernel.org/r/20230306140543.1813621-50-angelogioacchino.delregno@collabora.comSigned-off-by:
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AngeloGioacchino Del Regno authored
Bootloaders must in a way setup the SoC to boot Linux: this means that it will be possible to decompress a ramdisk and eventually insert the core clock driver module from there. Allow module build for all MT8192 clocks by switching to tristate. Signed-off-by:
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AngeloGioacchino Del Regno authored
This is the last man standing in clk-mt8192.c that won't allow us to use the module_platform_driver() macro, and for *no* good reason. Move it to clk-mt8192-apmixedsys.c and while at it, also add a .remove() callback for it. Also, since the need for "clk-mt8192-simple" and "clk-mt8192" was just due to them being in the same file and probing different clocks, and since now there's just one platform_driver struct per file, it seemed natural to rename the `-simple` variant to just "clk-mt8192". Signed-off-by:
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AngeloGioacchino Del Regno authored
When building clock drivers for MT8186, some may want to build in only some of them to, for example, get CPUFreq up faster, and some may want to leave out some clock drivers entirely as a machine may not need the Warp Engine or the camera ISP (hence, their clock drivers). Split the various clock drivers in their own configuration options, keeping MT8186 configuration options consistent with other MediaTek SoCs. While at it, also allow building the remaining clock drivers as modules by switching COMMON_CLK_MT8186 to tristate. Signed-off-by:
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AngeloGioacchino Del Regno authored
Most of the MT6797 clock drivers can be built as modules: change them to tristate to allow that. Signed-off-by:
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AngeloGioacchino Del Regno authored
Most of the MT6765 clock drivers can be built as modules: change them to tristate to allow that. Signed-off-by:
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AngeloGioacchino Del Regno authored
All MT8183 clocks are platform drivers now! Allow module build for all of them. Signed-off-by:
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AngeloGioacchino Del Regno authored
Almost all MT8167 clocks have been converted to use the common probe mechanism, moreover, now all of them are platform drivers: allow building as modules. Signed-off-by:
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AngeloGioacchino Del Regno authored
Now that all drivers are using the simple probe mechanism change the MT7622 clock drivers to tristate in Kconfig to allow module build. Signed-off-by:
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AngeloGioacchino Del Regno authored
Allow building non boot critical clocks for MT8192 SoC as modules by changing them to tristate. Signed-off-by:
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AngeloGioacchino Del Regno authored
MT8195 clock drivers were encapsulated in one single (and big) Kconfig option: there's no reason to do that, as it is totally unnecessary to build in all or none of them. Split them out: keep boot-critical clocks as bool and allow choosing non critical clocks as tristate. As a note, the dependencies of VDEC/VENCSYS and CAM/IMG/IPE/WPESYS are not for build-time but rather for runtime, as clocks registered by those have runtime dependencies on either or both VPP and IMGSYS. Signed-off-by:
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AngeloGioacchino Del Regno authored
All of the mt2712 drivers have been converted to platform drivers! Change the Kconfig options for all MT2712 clocks to tristate to allow building all clock drivers as modules. Signed-off-by:
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