- 10 Jul, 2020 1 commit
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Marek Olšák authored
It's impossible to debug shader hangs with soft recovery. Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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- 08 Jul, 2020 32 commits
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Tom Rix authored
clang static analysis flags this error drivers/gpu/drm/radeon/ci_dpm.c:5652:9: warning: Use of memory after it is freed [unix.Malloc] kfree(rdev->pm.dpm.ps[i].ps_priv); ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/radeon/ci_dpm.c:5654:2: warning: Attempt to free released memory [unix.Malloc] kfree(rdev->pm.dpm.ps); ^~~~~~~~~~~~~~~~~~~~~~ problem is reported in ci_dpm_fini, with these code blocks. for (i = 0; i < rdev->pm.dpm.num_ps; i++) { kfree(rdev->pm.dpm.ps[i].ps_priv); } kfree(rdev->pm.dpm.ps); The first free happens in ci_parse_power_table where it cleans up locally on a failure. ci_dpm_fini also does a cleanup. ret = ci_parse_power_table(rdev); if (ret) { ci_dpm_fini(rdev); return ret; } So remove the cleanup in ci_parse_power_table and move the num_ps calculation to inside the loop so ci_dpm_fini will know how many array elements to free. Fixes: cc8dbbb4 ("drm/radeon: add dpm support for CI dGPUs (v2)") Signed-off-by:Tom Rix <trix@redhat.com> Signed-off-by:
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Tiezhu Yang authored
When I update the latest kernel, I see the following "____ptrval____" boot messages. [ 1.872600] radeon 0000:01:05.0: fence driver on ring 0 use gpu addr 0x0000000048000c00 and cpu addr 0x(____ptrval____) [ 1.879095] radeon 0000:01:05.0: fence driver on ring 5 use gpu addr 0x0000000040056038 and cpu addr 0x(____ptrval____) Both radeon_fence_driver_start_ring() and amdgpu_fence_driver_start_ring() have the similar issue, there exists the following two methods to solve it: (1) Use "%pK" instead of "%p" so that the CPU address can be printed when the kptr_restrict sysctl is set to 1. (2) Just completely drop the CPU address suggested by Christian, because the CPU address was useful in the past, but isn't any more. We now have a debugfs file to read the current fence values. Since the CPU address is not much useful, just remove the debug info about CPU address. Reviewed-by:
Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] To support inbox1 in CW4 we need to actually program CW4 instead of region 4 for newer firmware. This is done correctly on DCN20/DCN21 but this code wasn't added to DCN30. [How] Copy over the missing code. It doesn't need address translation since DCN30 uses virtual addressing. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Huang Rui authored
This patch updates to use register distance member instead of hardcode in mmhub v9.4. Signed-off-by:
Huang Rui <ray.huang@amd.com> Tested-by:
AnZhong Huang <anzhong.huang@amd.com> Reviewed-by:
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Huang Rui authored
This patch updates to use register distance member instead of hardcode in mmhub v2. Signed-off-by:
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Huang Rui authored
This patch updates to use register distance member instead of hardcode in mmhub v1. Signed-off-by:
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Huang Rui authored
This patch updates to use register distance member instead of hardcode in gfxhub v2.1. Signed-off-by:
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Huang Rui authored
This patch updates to use register distance member instead of hardcode in gfxhub v2. Signed-off-by:
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Huang Rui authored
This patch updates to use register distance member instead of hardcode in gfxhub v1. Signed-off-by:
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Huang Rui authored
This patch updates to use register distance member instead of hardcode in VCN2/JEPG2. They are for the same ASIC. Signed-off-by:
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Huang Rui authored
This patch updates to use register distance member instead of hardcode in UVD7/VCE4. They are for the same ASIC. Signed-off-by:
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Huang Rui authored
This patch updates to use register distance member instead of hardcode in VCN1/JEPG1. They are for the same ASIC. Signed-off-by:
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Huang Rui authored
This patch updates to use register distance member instead of hardcode in GMC10. Signed-off-by:
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Huang Rui authored
This patch updates to use register distance member instead of hardcode in GMC9. Signed-off-by:
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Huang Rui authored
This patch is to abstract register distances between two continuous context domains and invalidation engines. In different ip headers, these distances may be differences. Signed-off-by:
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Felix Kuehling authored
kfd_pasid.c isn't using the kfd2kgd interface any more. Remove redundant code trying to look up a device for finding that interface. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Kent Russell <kent.russell@amd.com> Signed-off-by:
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Alex Jivin authored
Move the mutext lock/unlock outside of the if(), as the mutex is always taken: either in the if() branch or in the else branch. Signed-off-by:
Alex Jivin <alex.jivin@amd.com> Suggested-By:
Luben Tukov <luben.tuikov@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
This field is missing for dcn3 so add it from dcn20. enc2_set_dynamic_metadata() trys to sets this and we get a generic_reg warning since the mask is not defined. Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Wesley Chalmers authored
[WHY] We want to be able to see SMU messages sent and their responses Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
Joshua Aberback <Joshua.Aberback@amd.com> Acked-by:
Eryk Brol <eryk.brol@amd.com> Acked-by:
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Joshua Aberback authored
[Why] Currently we don't explicitly send a request for a minimum PHYCLK, and we hope that the dependencies other clocks have will raise PHYCLK when needed. [How] - new clk_mgr function to keep track of PHYCLK requirements - request maximum requirement across all links - remove PHYCLK from clock state comparator, as it doesn't come from DML Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Anthony Koo authored
[Header Changes] - Drop unused firmware SCRATCH bits from interface Signed-off-by:
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Roman Li authored
[Why] VSC infoframe is needed for PSR. Previously only DMCU controller supported PSR. Now DMUB also implements PSR. [How] Remove VSC infoframe dependency on DMCU. Signed-off-by:
Roman Li <roman.li@amd.com> Reviewed-by:
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Jaehyun Chung authored
[Why] Current DAL behaviour is to not send VSIF if mode does not support VRR (ie. FS range is < 10Hz). However, we should still set FS Native Color Active bit in some unsupported mode cases. [How] Remove check for if VRR is supported before building infopacket. Signed-off-by:
Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by:
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Igor Kravchenko authored
[Why] Driver re-initialize registers already set in FW [How] Transfer init to FW Signed-off-by:
Igor Kravchenko <Igor.Kravchenko@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Print scaling parameters as they are calculated in diags. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Likun Gao authored
MMHUB powergating should be disabled on navi12 and enabled on sienna cichlid. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Likun Gao authored
Use RREG32_KIQ to read gfx register when try to get gfx/sdma clockgating state instead of RREG32, as it will result to system hard hang when GPU is enter into GFXOFF state. Signed-off-by:
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John Clements authored
add support for loading ucode with ta_firmware_header_v2_0 Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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John Clements authored
added definition for ta_firmware_header_v2_0 Reviewed-by:
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Huang Rui authored
TMR is required to be destoried with GFX_CMD_ID_DESTROY_TMR while the system goes to suspend. Otherwise, PSP may return the failure state (0xFFFF007) on Gfx-2-PSP command GFX_CMD_ID_SETUP_TMR after do multiple times suspend/resume. Signed-off-by:
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Huang Rui authored
Unload ASD function in suspend phase. Signed-off-by:
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- 02 Jul, 2020 7 commits
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Colin Ian King authored
The variable result is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Alex Deucher authored
Large clock values may overflow and show up as negative. Reported by prOMiNd on IRC. Acked-by:
Nirmoy Das <nirmoy.das@amd.com> Signed-off-by:
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Alex Deucher authored
Add support for integrated_system_info table v12. Use the actual v12 structure. Acked-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
Used for renoir. Acked-by:
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Alex Deucher authored
Renoir uses integrated_system_info table v12. The table has the same layout as v11 with respect to this data. Just reuse the existing code for v12 for stable. Fixes incorrectly reported vram info in the driver output. Acked-by:
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Evan Quan authored
Fix the compile error below: drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c: In function 'smu_v11_0_init_microcode': >> arch/arc/include/asm/bug.h:22:2: error: implicit declaration of function 'pr_warn'; did you mean 'pci_warn'? [-Werror=implicit-function-declaration] 22 | pr_warn("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \ | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:176:3: note: in expansion of macro 'BUG' 176 | BUG(); Reported-by:kernel test robot <lkp@intel.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Changes that are fast don't require updating DLG parameters making this call unnecessary. Considering this is an expensive call it should not be done on every flip. DML touches clocks, p-state support, DLG params and a few other DC internal flags and these aren't expected during fast. A hang has been reported with this change when called on every flip which suggests that modifying these fields is not recommended behavior on fast updates. [How] Guard the validation to only happen if update type isn't FAST. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1191 Fixes: a24eaa5c ("drm/amd/display: Revalidate bandwidth before commiting DC updates") Signed-off-by:
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