- 14 Jul, 2017 40 commits
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Rex Zhu authored
Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Rex Zhu authored
1. simplify avfs state switch. 2. delete save/restore VFT table functions as not support by fiji. 3. implement thermal_avfs_enable funciton. Signed-off-by:
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Rex Zhu authored
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Evan Quan authored
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Evan Quan <evan.quan@amd.com> Reviewed-by:
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Huang Rui authored
In previous case, driver can't enable psp via the kernel parameter for raven. We should open this path and set it as direct by default till psp firmware loading is workable. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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Huang Rui authored
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Christian König <christian.koenig@amd.com> Reviewed-by:
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Huang Rui authored
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Huang Rui authored
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Shaoyun Liu authored
nbio hdp flush routine are called within atomic context. Avoid use KIQ when write to the HDP_MEM_COHERENCY_FLUSH_CNTL register since this register has its own VF copy Signed-off-by:
Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by:
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Shaoyun Liu authored
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Monk Liu authored
for SR-IOV, we must keep the pipeline-sync in the protection of COND_EXEC, otherwise the command consumed by CPG is not consistent when world switch triggerd, e.g.: world switch hit and the IB frame is skipped so the fence won't signal, thus CP will jump to the next DMAframe's pipeline-sync command, and it will make CP hang foever. after pipelin-sync moved into COND_EXEC the consistency can be guaranteed Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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Evan Quan authored
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Evan Quan authored
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Ken Wang authored
Certain MC registers need a delay after writing them to properly update in the init sequence. Signed-off-by:
Ken Wang <Ken.Wang@amd.com> Reviewed-by:
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Alex Deucher authored
Check the atom scratch registers to see if asic_init is complete or not. Reviewed-by:
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Alex Deucher authored
Now that we use a pointer to the scratch reg start offset, most of the functions were duplicated. Acked-by:
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Alex Deucher authored
Align with the atomfirmware code. Acked-by:
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Arvind Yadav authored
ttm_place are not supposed to change at runtime. All functions working with ttm_place provided by <drm/ttm/ttm_placement.h> work with const ttm_place. So mark the non-const structs as const. Reviewed-by:
Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by:
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Arvind Yadav authored
drm_prop_enum_lists are not supposed to change at runtime. All functions working with drm_prop_enum_list provided by <drm/drm_property.h> work with const drm_prop_enum_list. So mark the non-const structs as const. File size before: text data bss dec hex filename 18276 384 0 18660 48e4 drivers/gpu/drm/radeon/radeon_display.o File size After adding 'const': text data bss dec hex filename 18660 0 0 18660 48e4 drivers/gpu/drm/radeon/radeon_display.o Reviewed-by:
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Arvind Yadav authored
ttm_place are not supposed to change at runtime. All functions working with ttm_place provided by <drm/ttm/ttm_placement.h> work with const ttm_place. So mark the non-const structs as const. File size before: text data bss dec hex filename 9235 344 136 9715 25f3 drivers/gpu/drm/radeon/radeon_ttm.o File size After adding 'const': text data bss dec hex filename 9267 312 136 9715 25f3 drivers/gpu/drm/radeon/radeon_ttm.o Reviewed-by:
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Christian König authored
Otherwise the upper bits are lost. Signed-off-by:
Alex Xie <AlexBin.Xie@amd.com> Reviewed-by:
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Christian König authored
That is already fixed. Signed-off-by:
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Nicolai Hähnle authored
This makes it easier to correlate amd_sched_job with with other trace points that don't log the job pointer. v2: don't print the sched_job pointer (Andres) Signed-off-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by:
Andres Rodriguez <andresx7@gmail.com> Reviewed-by:
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Hawking Zhang authored
Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Huang Rui authored
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Christian König authored
This avoids binding them later on. v2: fix typo in function name Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com>
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Christian König authored
No need to do this on every round. Signed-off-by:
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Christian König authored
This allows us to flush the system VM here. Signed-off-by:
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Christian König authored
This allows us to queue IBs which needs an up to date system domain as well. Signed-off-by:
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Christian König authored
Overwriting still used ring content has a low probability to cause problems, not writing at all has 100% probability to cause problems. Signed-off-by:
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Christian König authored
Keep them where they belong. Signed-off-by:
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Gustavo A. R. Silva authored
Add function header comment to make it clear that local variable sw_cg is used for debugging and it should not be removed. Addresses-Coverity-ID: 1198635 Cc: Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by:
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Kent Russell authored
This was updated to 512 and the description update got missed Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
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ozeng authored
With previous golden settings, compute task can't use reserved LDS (32K) on CU0 and CU1. On 64K LDS system, if compute work group allocate more than 32K LDS, then it can't be dispatched to CU0 and CU1 because of the reservation. This enables compute task to use reserved LDS on CU0 and CU1. Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Acked-by:
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Christian König authored
Otherwise we trigger a bunch of WARN_ONs when this is called. Signed-off-by:
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Christian König authored
Stop spreading the code over all GMC generations. Signed-off-by:
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