- 21 Oct, 2015 4 commits
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Junwei Zhang authored
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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Christian König authored
Finally getting rid of it. Signed-off-by: Christian König <christian.koenig@amd.com>
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Christian König authored
It didn't worked to well anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
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Geliang Tang authored
s/regsiter/register/ Signed-off-by: Geliang Tang <geliangtang@163.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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- 19 Oct, 2015 2 commits
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Alex Deucher authored
We were basically opencoding the same thing in both hw_init and resume and hw_fini and suspend. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This is the recommended setting from the hw team for newer versions of the firmware. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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- 15 Oct, 2015 1 commit
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Daniel Vetter authored
This removes the last depency of radeon for dev->struct_mutex! Also the locking scheme for hyperz/cmask owners seems a bit unsound, there's no protection in the preclose handler (and that never did hold dev->struct_mutex while being called). So grab the same lock there, too. There's also all the checks in the cs checker, but since the overall design seems to never stall for the previous owner I figured it's ok if I leave this racy. It was racy even before I touched it after all too. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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- 14 Oct, 2015 31 commits
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Junwei Zhang authored
The first lockup fence will lock the fence list of scheduler. Then cancel the delayed workqueues for all clean pending fences without waiting the workqueues to finish. Change-Id: I9bec826de1aa49d587b0662f3fb4a95333979429 Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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Junwei Zhang authored
Change-Id: I67e987db0efdca28faa80b332b75571192130d33 Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: David Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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Christian König authored
Output all VM mappings a command submission uses. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
This makes it much easier to find when userspace misses to send some buffers. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Port of radeon commit 9b7d786b. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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Lukas Wunner authored
This was added to two radeon files even though they don't use any vga_switcheroo symbols, the amdgpu fork inherited them: Added to amdgpu_acpi.c by commit d7a2952f ("drm/radeon: Add support for the ATIF ACPI method to the radeon driver"). Added to amdgpu_bios.c by commit 6a9ee8af ("vga_switcheroo: initial implementation (v15)"). Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Lukas Wunner authored
This was added to three files even though they don't use any vga_switcheroo symbols: Added to radeon_acpi.c by commit d7a2952f ("drm/radeon: Add support for the ATIF ACPI method to the radeon driver"). Added to radeon_asic.c by commit 0a10c851 ("drm/radeon: create radeon_asic.c"). Added to radeon_bios.c by commit 6a9ee8af ("vga_switcheroo: initial implementation (v15)"). Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Check to make sure we aren't touching a non-existent display controller and simplify the code. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Rework the sdma structures in the driver to consolidate all of the sdma info into a single structure and allow for asics that may have different numbers of sdma instances. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Everything is evicted from VRAM before suspend, so we need to make sure all BOs are unpinned and re-pinned after resume. Fixes broken mouse cursor after resume introduced by commit b9729b17. Port of radeon commit: f3cbb17bReviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Port of radeon commit: 8991668aReviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Take a GEM reference for and pin the new cursor BO, unpin and drop the GEM reference for the old cursor BO in dce8 crtc_cursor_set2, and use amdgpu_crtc->cursor_addr in dce8 set_cursor. This fixes dce8 cursor_reset accidentally incrementing the cursor BO pin count, and cleans up the code a little. Port of radeon commit: cd404af0Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
It's only needed in dce8 crtc_cursor_set2. Port of radeon commit: 2e007e61Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Setting a mode seems to clear the cursor registers, so we need to re-program them to make sure the cursor is visible. Port of radeon commit: 6d3759fa v2: change radeon reference in error message Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
The cursor_set2 hook provides the cursor hotspot position within the cursor image. When the hotspot position changes, we can adjust the cursor position such that the hotspot doesn't move on the screen. This prevents the cursor from appearing to intermittently jump around on the screen when the position of the hotspot within the cursor image changes. Port of radeon commits: 78b1a601 3feba08dReviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Port of radeon commit: 8991668aReviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Take a GEM reference for and pin the new cursor BO, unpin and drop the GEM reference for the old cursor BO in dce11 crtc_cursor_set2, and use amdgpu_crtc->cursor_addr in dce11 set_cursor. This fixes dce11 cursor_reset accidentally incrementing the cursor BO pin count, and cleans up the code a little. Port of radeon commit: cd404af0Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
It's only needed in dce11 crtc_cursor_set2. Port of radeon commit: 2e007e61Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Setting a mode seems to clear the cursor registers, so we need to re-program them to make sure the cursor is visible. Port of radeon commit: 6d3759fa v2: change radeon reference in error output Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
The cursor_set2 hook provides the cursor hotspot position within the cursor image. When the hotspot position changes, we can adjust the cursor position such that the hotspot doesn't move on the screen. This prevents the cursor from appearing to intermittently jump around on the screen when the position of the hotspot within the cursor image changes. Port of radeon commits: 78b1a601 3feba08dReviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Port of radeon commit: 8991668aReviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Take a GEM reference for and pin the new cursor BO, unpin and drop the GEM reference for the old cursor BO in dce10 crtc_cursor_set2, and use amdgpu_crtc->cursor_addr in dce10 set_cursor. This fixes dce10 cursor_reset accidentally incrementing the cursor BO pin count, and cleans up the code a little. Port of radeon commit: cd404af0Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
It's only needed in dce10 crtc_cursor_set2. Port of radeon commit: 2e007e61Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Setting a mode seems to clear the cursor registers, so we need to re-program them to make sure the cursor is visible. Port of radeon commit: 6d3759fa v2: change radeon reference in error message Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
The cursor_set2 hook provides the cursor hotspot position within the cursor image. When the hotspot position changes, we can adjust the cursor position such that the hotspot doesn't move on the screen. This prevents the cursor from appearing to intermittently jump around on the screen when the position of the hotspot within the cursor image changes. Port of radeon commits: 78b1a601 3feba08dReviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Better precision than the regular div opcode. v2: drop 64 bit divide v3: fix op handling. This actually is a 64 bit divide. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Better precision than the regular mul opcode. v2: handle big endian properly. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Just skips a data section. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Basically a nop. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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- 08 Oct, 2015 2 commits
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Alex Deucher authored
These are buggy on some asics and not really used anymore now that the GPU schedular is enabled. Change-Id: I67182b409d64de308392a15d1a0a15018071dc0b Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Chunming Zhou authored
Change-Id: Idce64f63e8422324996fc5d583d0bc9a5ac60d0c Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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