- 21 Mar, 2016 9 commits
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Jani Nikula authored
Makes it neater to add the same for DSI transcoder. No functional changes. v2: rename to hsw_get_transcoder_state and add a comment about grabbing power reference (Ville) Reviewed-by:Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/c473a73d69dcd61584419d85ff7908a8717b0594.1458313400.git.jani.nikula@intel.com
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Jani Nikula authored
Prep work for DSI transcoders. No functional changes. v2: call split functions at a higher level (Ville) Reviewed-by:
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Jani Nikula authored
Prep work for DSI transcoders. No functional changes. v2: call split functions at a higher level (Ville) Reviewed-by:
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Jesse Barnes authored
Some configs use the P2X type but some use a P3X type PCH, so add that to the detect_pch function so things work correctly. Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by:
Allen Kay <allen.m.kay@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1458160290-16710-1-git-send-email-jbarnes@virtuousgeek.org
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Jordan Justen authored
Signed-off-by:
Jordan Justen <jordan.l.justen@intel.com> Reviewed-by:
Francisco Jerez <currojerez@riseup.net> Signed-off-by:
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Jordan Justen authored
This is needed for the Mesa Vulkan driver on Haswell. Signed-off-by:
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Jordan Justen authored
Now that we can whitelist registers only on Haswell, move HSW_SCRATCH1 and HSW_ROW_CHICKEN3 into a separate Haswell only table. Signed-off-by:
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Jordan Justen authored
For Haswell, we will want another table of registers while retaining the large common table of whitelisted registers shared by all gen7 devices. Signed-off-by:
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Jordan Justen authored
This is needed for the Mesa Vulkan driver on Haswell. Signed-off-by:
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- 18 Mar, 2016 9 commits
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Imre Deak authored
Atm, in case failure injection forces an error the subsequent "*ERROR* failed to init modeset" error message will make automated tests (CI) report this event as a breakage even though the event is expected. To fix this print the error message with debug log level in this case. While at it print the error message for any init failure and change it to """ Device initialization failed (errno) Please file a bug at https://bugs.freedesktop.org/enter_bug.cgi?product=DRI against DRM/Intel providing the dmesg log by booting with drm.debug=0xf """ and export a helper printing error messages using this same format. A follow-up patch will convert all uses of DRM_ERROR reporting a user facing problem to use this new helper instead. v2: - Include the problematic error message in the commit log, add a request to file an fdo bug to the message (Chris) v3: - Include the new error message too in the commit log, make the fdo link more precise and print part of the message with info log level (Chris) v4: (Chris) - Use dev_printk instead of DRM_ERROR/INFO and use NOTICE instead of INFO loglevel - Export a helper for printing user facing error messages v5: - Keep the DRM_ERROR message prefix used by piglit-igt/CI to filter relevant dmesg lines - Use dev_notice(), instead of dev_printk(KERN_NOTICE,...) v6: - Print the fdo bug link only once (Chris) CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/1458290770-15480-1-git-send-email-imre.deak@intel.com
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Chris Wilson authored
Throughout the code base, we use u32 for offsets into the global GTT. If we ever see any hardware with a larger GGTT, then we run the real risk of silent corruption. So test for our assumption up front so that we have a nice reminder should the time come when it fails. Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> [Rebased and changed 1ull -> 1ULL, cut 80 char line] Reviewed-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by:
Mika Kuoppala <mika.kuoppala@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458290579-27783-1-git-send-email-joonas.lahtinen@linux.intel.com
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Joonas Lahtinen authored
Use less pointers with the probing code, making it much less confusing to read. Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by:
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Joonas Lahtinen authored
Refer to Global GTT consistently as GGTT, thus rename dev_priv->gtt to dev_priv->ggtt and struct i915_gtt to struct i915_ggtt. Fix a couple of whitespace problems while at it. v2: - Fix a typo in commit message. Reviewed-by:
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Joonas Lahtinen authored
Reference variable value from pointer, not assumed pointer destination. Since: commit c44ef60e Author: Mika Kuoppala <mika.kuoppala@linux.intel.com> Date: Thu Jun 25 18:35:05 2015 +0300 drm/i915/gtt: Allow >= 4GB sizes for vm. Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by:
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Tim Gore authored
This allows writes to EU flow control registers. Together with SIP code from the user-mode driver this resolves a hang seen in some pre-emption scenarios. Note that this patch is just the kernel mode part of this workaround. v2. Oops, add FLOW_CONTROL_ENABLE macro to i915_reg.h. Signed-off-by:
Tim Gore <tim.gore@intel.com> Reviewed-by:
Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by:
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Tvrtko Ursulin authored
By reading the CSB (slow MMIO accesses) into a temporary local buffer we can decrease the duration of holding the execlist lock. Main advantage is that during heavy batch buffer submission we reduce the execlist lock contention, which should decrease the latency and CPU usage between the submitting userspace process and interrupt handling. Downside is that we need to grab and relase the forcewake twice, but as the below numbers will show this is completely hidden by the primary gains. Testing with "gem_latency -n 100" (submit batch buffers with a hundred nops each) shows more than doubling of the throughput and more than halving of the dispatch latency, overall latency and CPU time spend in the submitting process. Submitting empty batches ("gem_latency -n 0") does not seem significantly affected by this change with throughput and CPU time improving by half a percent, and overall latency worsening by the same amount. Above tests were done in a hundred runs on a big core Broadwell. v2: * Overflow protection to local CSB buffer. * Use closer dev_priv in execlists_submit_requests. (Chris Wilson) v3: Rebase. v4: Added commend about irq needed to be disabled in execlists_submit_request. (Chris Wilson) Signed-off-by: -
Tvrtko Ursulin authored
Where we have a request we can use req->i915 directly instead of going through the engine and device. Coccinelle script: @@ function f; identifier r; @@ f(..., struct drm_i915_gem_request *r, ...) { ... - engine->dev->dev_private + r->i915 ... } @@ struct drm_i915_gem_request *req; @@ ( req-> - engine->dev->dev_private + i915 ) Signed-off-by: -
Tvrtko Ursulin authored
Signed-off-by:
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- 17 Mar, 2016 22 commits
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Imre Deak authored
Add support for forcing an error at selected places in the driver. As an example add 4 options to fail during driver loading. Requested by Chris. v2: - Add fault point for modeset initialization - Print debug message when injecting an error v3: - Rename inject_fault to inject_load_failure, rename the related macros and helper accordingly (Chris) - Use a counter instead of a mask to identify the failure point (Daniel) - Mark the module option as _unsafe and keep i915_params ordered (Joonas) v4: - Rebase on latest -nightly v5: - Use DRM_INFO instead of DRM_DEBUG_DRIVER, making it clearer in CI reports that a following error message is expected (IRC r-b from Chris on v5) CC: Chris Wilson <chris@chris-wilson.co.uk> CC: Daniel Vetter <daniel.vetter@ffwll.ch> CC: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by:
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Imre Deak authored
Move the cleanup of the power domain HW state on the error path to the same function where the corresponding init call was called from. I noticed this problem when loading the module with load failure injection enabled, making i915_load_modeset_init() fail. CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Imre Deak authored
According to the new init phases scheme we should register the device making it available via some kernel internal or user space interface as the last step in the init sequence, so move the corresponding code to a separate function. Also add a TODO comment about code that still needs to be moved around to one of the init phases functions depending on what the role and effect of that code is. No functional change, except for the reordering of the unload time unregistration steps of sysfs wrt. acpi and opregion. Suggested by Chris. v3: - rename i915_driver_init_register to i915_driver_init_frameworks (Chris) - rename i915_driver_init_frameworks to i915_driver_register (Daniel) CC: Chris Wilson <chris@chris-wilson.co.uk> CC: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Imre Deak authored
According to the new init phases scheme we should have a definite step in the init sequence where we setup things requiring accessing the device, so move the corresponding code to separate function. The steps in this init phase should avoid exposing the driver via some interface, which is done in the last registration init phase. This changae also has the benefit of making the error path cleaner both in the new function and i915_driver_load()/unload(). No functional change. Suggested by Chris. CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Imre Deak authored
According to the new init phases scheme we should have a definite step in the init sequence where MMIO access is setup, so move the corresponding code to a separate function. This also has the benefit of making the error path cleaner both in the new function and in i915_driver_load()/unload(). No functional change. Suggested by Chris. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Imre Deak authored
According to the new init phases scheme we should initialize "SW-only" state not requiring accessing the device as the very first step, so that the reasoning about dependencies of later steps becomes easier. So move these init steps into a separate function. This also has the benefit of making the error path cleaner both in the new function and int i915_driver_load()/unload(). No functional change. Suggested by Chris. CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Imre Deak authored
Move the opregion unregistration earlier to match its corresponding registration order. Signed-off-by:
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Imre Deak authored
Move the GTT,MSI IRQ cleanup later so that it matches their corresponding init order. Also fix the order of these calls wrt. each other to match their corresponding init order. Signed-off-by:
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Imre Deak authored
Move the power domain uninitialization later so that it matches its corresponding init order. Since we access the HW during the later unitialization steps keep a wake reference until after the last such step. Signed-off-by:
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Imre Deak authored
We should register all the interfaces before we enable runtime PM. Signed-off-by:
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Imre Deak authored
According to the new init phases scheme we should register the driver with frameworks/userspace only one the device is setup fully. So move the shrinker registration later accordingly. Also fix the shrinker unregistration order wrt. the acpi unregistration to fix the corresponding init order. Signed-off-by:
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Imre Deak authored
We require the device to be powered only before accessing it, so we can move this call later. Signed-off-by:
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Imre Deak authored
The only steps requiring device access is the fence and swizzling initialization, so split these out keeping them in their current place and move the rest of init steps earlier. v2-v3: - unchanged v4: - move call to i915_gem_detect_bit_6_swizzle() to i915_gem_load_init_fences() and preserve the original order of the detection of HW fence capailities wrt. swizzling (Chris) CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Imre Deak authored
This init step accesses the device, but doesn't have any device specific side effect. It also sets up some platform specific attributes that may be required early, so move it earlier. Signed-off-by:
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Imre Deak authored
Split out the part initing the clock gating hooks and move it earlier. Add a new NOP hook for platforms without the need to apply clockgating or workaround settings, so that the hook can be called unconditionally. Also add a WARN for future platforms that forget to add a hook. The rest of the hooks in intel_init_pm() should be inited in the same way, but atm some of the hooks are set only conditionally, so before doing this we need to make the setup unconditional and use instead some flags. v2: - add a NOP hook and WARN if no hook is set for the platform (Chris) - use the term hook instead of callback for these functions (Jani) v3: - remove the GEN4() check it's already covered by earlier platform checks (Chris) CC: Jani Nikula <jani.nikula@intel.com> CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Imre Deak authored
All of this is SW only initialization so we can move them earlier. Move the mutex init where the rest of the locks are inited. While at it also convert dev to dev_priv. v2: - use the term hook instead of callback for these functions (Jani) CC: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Imre Deak authored
Most of the IRQ init is setting up hooks so move that part earlier. Leave the pm_qos_add_request() call in place. Signed-off-by:
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Imre Deak authored
These are all SW only init steps not accessing the device and they only need the platform identification macros to work, which are already available earlier, so move these init steps earlier. Signed-off-by:
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Imre Deak authored
MCHBAR is cleaned up in i915_mmio_cleanup(), so the separate call in i915_driver_load() is incorrect. CC: David Weinehall <david.weinehall@intel.com> Fixes: ad5c3d3f ("drm/i915: Move MCHBAR setup earlier during init") Signed-off-by:
David Weinehall <david.weinehall@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458128348-15730-2-git-send-email-imre.deak@intel.com
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Mika Kuoppala authored
In full gpu reset we prime all engines and reset domains corresponding to each engine. Per engine reset is just a special case of this process wherein only a single engine is reset. This change is aimed to modify relevant functions to achieve this. There are some other steps we carry out in case of engine reset which are addressed in later patches. Reset func now accepts a mask of all engines that need to be reset. Where per engine resets are supported, error handler populates the mask accordingly otherwise all engines are specified. v2: ALL_ENGINES mask fixup, better for_each_ring_masked (Chris) v3: Whitespace fixes (Chris) v4: Rebase due to s/ring/engine Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Jani Nikula authored
We've been accumulating code across the driver that depends on the VBT specific structures and defines. The VBT is an uncontrollable beast. Encourage encapsulation of the VBT data by hiding the structures and defines in a private header only to be included from intel_bios.c. Reviewed-by:
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Jani Nikula authored
drivers/gpu/drm/i915/intel_dpll_mgr.c:1200:32: warning: Using plain integer as NULL pointer Fixes: 304b65cb ("drm/i915: Move SKL/KLB pll selection logic to intel_dpll_mgr.c") Reviewed-by:
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