- 01 Jul, 2020 40 commits
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Jay Cornwall authored
The contents of macros are parsed by the assembler before conditions have been tested. This causes assembly errors when using IP-specific instructions in the IP-unified trap handler. Add a preprocessing step to filter IP-specific code. Also guard a Navi1x-specific instruction (no effect on Sienna_Cichlid). Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Reviewed-by:
Yong Zhao <Yong.Zhao@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jay Cornwall authored
- Replace SQC stores with TCP stores - Synchronize with MSG_SAVEWAVE via lgkmcnt - HW_REG_IB_STS is now read-only Signed-off-by:
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Yong Zhao authored
v4: drop get_tile_config, comment out other callbacks Signed-off-by:
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Jerry (Fangzhi) Zuo authored
Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Likun Gao authored
Only disable 3D pipe 1 on navi1x, enable 3D pipe 1 on Sienna_Cichlid. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Likun Gao authored
Each of HDP flush engine should be used by one ring, correct allocate of hdp flush engine to SDMA ring. Correct me value of each SDMA ring, as it was cleared when init microcode. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Likun Gao authored
Enable mmhub clockgating. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Kenneth Feng authored
athub ls is bounded with hdp ls,verified. Signed-off-by:
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Kenneth Feng authored
IH cg verified Signed-off-by:
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Kenneth Feng authored
add HDP mgcg and ls support and verified Signed-off-by:
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Kenneth Feng authored
confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to be set for SRAM LS/DS/SD Signed-off-by:
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Likun Gao authored
Update gfx golden setting for gfx10.3. Signed-off-by:
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Leo Liu authored
So the LMI register will be programmed properly Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Leo Liu authored
for the second instance with correct index Signed-off-by:
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Leo Liu authored
The signed header is added Signed-off-by:
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Likun Gao authored
Open GFX MGCG, CGCG and 3DCG for sienna_cichlid. Signed-off-by:
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Hawking Zhang authored
For Sienna_Cichlid, query fw_reserved_fb_size from vbios directly. For navi1x, fall back to default 64K TMR size. For pre-navi, no need to reserve tmr region in top LFB. v2: fix TMR define (Alex) v3: partially revert size change Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Hawking Zhang authored
fw_reserved_size_in_kb is introduced for driver to query the TMR region reserved by PSP BL in Sienna_Cichlid and onwards Signed-off-by:
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Hawking Zhang authored
firmware_info v3_4 strucure will be used by kernel driver to query various parameters set by VBIOS for Sienna_Cichlid Signed-off-by:
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Likun Gao authored
As all four sdma firmware are same, PSP only receive one SDMA fw. Signed-off-by:
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Hawking Zhang authored
tiling mode table is not used anymore for gfx10 Signed-off-by:
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Hawking Zhang authored
support query vram_module v11 and vram_info v2_5 for sienna_cichlid Signed-off-by:
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Hawking Zhang authored
vram_info v2_5 was introduced to support sienna_cichlid Signed-off-by:
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Likun Gao authored
Temporary disable gfxoff for sienna_cichlid. Signed-off-by:
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Likun Gao authored
Triger CP ucode addr and data to backdoor load CP firmware. Signed-off-by:
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Hawking Zhang authored
pa_sc_tile_steering_override is only programmable for gfx10.0/10.1/10.2 Signed-off-by:
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Likun Gao authored
Add gc golden setting for sienna_cichlid. Signed-off-by:
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Leo Liu authored
By adding JPEG HW block to Sienna_Cichlid Signed-off-by:
James Zhu <James.Zhu@amd.com> Acked-by:
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Leo Liu authored
By setting up the flags to the ASIC Signed-off-by:
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Leo Liu authored
This is for static powergating and clockgating Signed-off-by:
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Leo Liu authored
With basic IP block functions and ring functions Signed-off-by:
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Leo Liu authored
By adding VCN HW block to Sienna_Cichlid Signed-off-by:
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Leo Liu authored
By adding Sienna_Cichlid VCN firmware Signed-off-by:
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Leo Liu authored
By setting up the flags to the ASIC Signed-off-by:
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Leo Liu authored
This is for static powergating and clockgating v2: fix registers (Alex) Signed-off-by:
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Leo Liu authored
With basic IP block functions and ring functions Signed-off-by:
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Likun Gao authored
Correct CP_MES_IC_OP_CNTL register address for sienna_cichlid on mes v10.1. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Signed-off-by:
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Likun Gao authored
The number of queue per pipe for mec on sienna_cichlid should be 4. Signed-off-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Jack Xiao authored
Add mes block support to sienna_cichlid. Signed-off-by:
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Jack Xiao authored
Update mes initialization sequence. Signed-off-by:
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