* hisi/soc:
  ARM: dts: rename hi4511 dts file
  ARM: hisi: remove init_time
  ARM: hisi: rename hi3xxx to hisi
  ARM: dts: enable clock binding on Hi3620
  ARM: hi3xxx: add hotplug support
  ARM: hi3xxx: add smp support
  ARM: config: add defconfig for Hi3xxx
  ARM: config: enable hi3xxx in multi_v7_defconfig
  ARM: dts: enable hi4511 with device tree
  ARM: hi3xxx: add board support with device tree
Signed-off-by: Kevin Hilman <khilman@linaro.org>

From Shawn Guo:
i.MX SoC changes for 3.14:
 - Add the initial i.MX50 SoC support
 - Support device tree boot for i.MX35
 - Move imx5 clock driver to use macros for clock ID
 - Some random updates and non-critical fixes on clock drivers
 - A few defconfig updates and minor cleanups

* tag 'imx-soc-3.14' of git://git.linaro.org/people/shawnguo/linux-2.6: (37 commits)
  ARM: imx: improve the comment of CCM lpm SW workaround
  ARM: imx: improve status check of clock gate
  ARM: imx: add necessary interface for pfd
  ARM: imx_v6_v7_defconfig: Select CONFIG_REGULATOR_PFUZE100
  ARM: imx_v6_v7_defconfig: Select MX35 and MX50 device tree support
  ARM: imx: Add cpu frequency scaling support
  ARM i.MX35: Add devicetree support.
  ARM: imx: update imx_v6_v7_defconfig
  ARM: imx6sl: Add missing spba clock to clock tree
  ARM: imx6sl: Add missing pll4_audio_div to the clock tree
  ARM: imx6: Derive spdif clock from pll3_pfd3_454m
  ARM: imx: use __initconst for const init definition
  ARM i.MX5: fix obvious typo in ldb_di0_gate clk definition
  ARM i.MX5: set CAN peripheral clock to 24 MHz parent
  ARM: imx: pllv1: Fix PLL calculation for i.MX27
  ARM i.MX5: fix "shift" value for lp_apm_sel on i.MX50 and i.MX53
  ARM: imx: imx53: Add SATA PHY clock
  ARM: imx_v6_v7_defconfig: Enable STMPE touchscreen
  ARM: imx: rename IMX6SL_CLK_CLK_END to IMX6SL_CLK_END
  ARM: imx: select PINCTRL at sub-architecure level
  ...
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'renesas-soc3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

From Simon Horman:
Third Round of Renesas ARM Based SoC Updates for v3.14

* Global
  - Don't set plat_sci_port scbrr_algo_id field
  - Declare SCIF register base and IRQ as resources
  - Don't define SCIF platform data in an array
  - Use macros to declare SCIF devices

* r7s72100 SoC (RZ/A1H)
  - Add i2c clocks

* r8a7778 (R-Car M1)
  - Add sound SCU clock support

* tag 'renesas-soc3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (43 commits)
  arm: shmobile: r7s72100: add i2c clocks
  ARM: shmobile: r8a7791: Don't set plat_sci_port scbrr_algo_id field
  ARM: shmobile: r8a7779: Don't set plat_sci_port scbrr_algo_id field
  ARM: shmobile: r8a7790: Don't set plat_sci_port scbrr_algo_id field
  ARM: shmobile: r8a7740: Don't set plat_sci_port scbrr_algo_id field
  ARM: shmobile: r8a73a4: Don't set plat_sci_port scbrr_algo_id field
  ARM: shmobile: r8a7778: Don't set plat_sci_port scbrr_algo_id field
  ARM: shmobile: r7s72100: Don't set plat_sci_port scbrr_algo_id field
  ARM: shmobile: sh73a0: Don't set plat_sci_port scbrr_algo_id field
  ARM: shmobile: r8a7790: Declare SCIF register base and IRQ as resources
  ARM: shmobile: r8a7791: Declare SCIF register base and IRQ as resources
  ARM: shmobile: r8a7778: Declare SCIF register base and IRQ as resources
  ARM: shmobile: sh7372: Don't set plat_sci_port scbrr_algo_id field
  ARM: shmobile: r8a7779: Declare SCIF register base and IRQ as resources
  ARM: shmobile: r8a7740: Declare SCIF register base and IRQ as resources
  ARM: shmobile: r8a73a4: Declare SCIF register base and IRQ as resources
  ARM: shmobile: r7s72100: Declare SCIF register base and IRQ as resources
  ARM: shmobile: sh73a0: Declare SCIF register base and IRQ as resources
  ARM: shmobile: sh7372: Declare SCIF register base and IRQ as resources
  ARM: shmobile: r8a7790: Don't define SCIF platform data in an array
  ...
Signed-off-by: Olof Johansson <olof@lixom.net>

* qcom/soc:
  ARM: msm: Simplify ARCH_MSM_DT config
  ARM: msm: Add support for MSM8974 SoC
  ARM: msm: trout: fix uninit var warning
Signed-off-by: Olof Johansson <olof@lixom.net>

This doesn't need to be a def_bool y. Instead we can have every
DT supported platform select ARCH_MSM_DT and we achieve the same
thing with less chance of conflicts.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>

Add support for the Snapdragon 800 MSM8974 SoC, used on the Dragonboard
and others. Board support added in separate patch.
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Acked-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
[olof: split off SoC support in separate patch]
Signed-off-by: Olof Johansson <olof@lixom.net>

Fix the following warning when !CONFIG_MMC:

arch/arm/mach-msm/board-trout.c: In function 'trout_init':
arch/arm/mach-msm/board-trout.c:67:6: warning: unused variable 'rc' [-Wunused-variable]
  int rc;
      ^

Also, while we're here, rework explicit printk(KERN_CRIT..) to use
pr_crit.
Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>

Improve the comment of SW workaround for CCM lpm issue using
hardware errata description to avoid confusion.

ERR007265: CCM: When improper low-power sequence is used, the SoC
enters low power mode before the ARM core executes WFI.

Software workaround:
1) Software should trigger IRQ #32 (IOMUX) to be always pending
   by setting IOMUX_GPR1_GINT.
2) Software should then unmask IRQ #32 in GPC before setting CCM
   Low-Power mode.
3) Software should mask IRQ #32 right after CCM Low-Power mode is
   set (set bits 0-1 of CCM_CLPCR).
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

For ccm clock gate, both 2b'11 and 2b'01 should be treated
as clock enabled, see below description in CCM, whenver CPU
trys to check clock gate's status, system will be in run mode.

2b'00: clock is off during all modes;
2b'01: clock is on in run mode, but off in wait and stop mode;
2b'10: Not applicable;
2b'11: clock is on during all modes, except stop mode.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Common clk framework will disable unused clks in late init only if
they are enabled by default and no one is using it, so we need to
add is_enabled callback for clk framework to get clks' status.

PFD clocks are enabled by hardware reset, so we need to add
interface for common clk framework to disable those unused ones for
saving power.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

PFUZE100 regulator is commonly found on mx6 based designs.

Add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Let MX35 and MX50 device tree support be built by default.

Generated by doing:

- Selected CONFIG_MACH_IMX35_DT and CONFIG_SOC_IMX50 via 'make menuconfig'
- make savedefconfig
- cp defconfig arch/arm/configs/imx_v6_v7_defconfig
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Re-using iMX6Q driver for cpu frequency scaling.
Signed-off-by: John Tobias <john.tobias.ph@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Cc: linux-arm-kernel@lists.infradead.org
Cc: Eric Bénard <eric@eukrea.com>
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Denis Carikli <denis@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Update the IMX v6/v7 defconfig for the SolidRun HummingBoard:
- Add AT803X ethernet phy
- Add consumer IR devices
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

We are missing spba clock in imx6sl's clock tree, thus add it.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

There's a dividor for pll4_audio clock missing in clock tree, thus add it.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

SPDIF can derive a TX clock for playback from one of its clock sources --
spdif root clock to match its supporting sample rates. So this patch set
the spdif root clock's parent to pll3_pfd3_454m since the pll3_pfd3_454m
can approximately meet its sample rate requirement.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

0-DAY kernel build testing backend reports the following.

 scripts/checkpatch.pl 0001-ARM-imx-add-support-code-for-IMX50-based-machines.patch
 # many are suggestions rather than must-fix

 ERROR: Use of const init definition must use __initconst
 #80: arch/arm/mach-imx/mach-imx50.c:26:
 +static const char *imx50_dt_board_compat[] __initdata = {

While at it, fix the error globally for IMX platform.
Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Acked-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

ldb_di0_gate is registerd with the clk index of IMX5_CLK_LDB_DI1_GATE,
thus the DI0 interface will be turned off inadvertently during boot.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

This patch sets the parent of CAN peripheral clock (a.k.a. CPI clock) to the
lp_apm clock, which has a rate of 24 MHz.

In the CAN world a base clock with multiple of 8 MHz is suited best for all CIA
recommented bit rates. Without this patch the CAN peripheral clock on i.MX53
has a rate of 66.666 MHz which produces quite large bit rate errors.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

MFN bit 9 on i.MX27 has a different meaning than in other SOCs. This
is a just sign bit. This patch makes different calculation for i.MX27.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

According to the i.MX50 Rev. 1 and i.MX53 Rev. 2.1 datasheet the lp_apm_sel is
bit 10 in the CCM_CCSR register not bit 9. On the i.MX51 it's bit 9.

This patch fixes this issue.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Add SATA PHY clock which are derived from the USB PHY1 clock. Note that this
patch derives the SATA PHY clock from USB PHY1 clock gate so that the SATA
driver can ungate both the SATA PHY clock and USB PHY1 clock for the SATA to
work correctly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Richard Zhu <r65037@freescale.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Linux-IDE <linux-ide@vger.kernel.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Enable STMPE touchscreen support as this is used on M53EVK.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

The macro name IMX6SL_CLK_CLK_END is a little insane.  Rename it to
IMX6SL_CLK_END.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Instead of selecting PINCTRL on individual SoC, let's select it at IMX
sub-architecure level.

While at it, it also adds the missing PINCTRL_IMX50 selection for
SOC_IMX50.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

ARM clock is sourcing from pll1_sw, and pll1_sw can be either from
pll1_sys or step, so we should enable arm clock during clock
initialization instead of pll1_sys, otherwise, arm clock's usecount
would be incorrect and PLL1 will never be disabled even it is not
used.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Use clock defines in order to make devicetrees more
human readable.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Merge tag 'renesas-soc2-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

From Simon Horman:
Second Round of Renesas ARM Based SoC Updates for v3.14

* Global
  - Add select MIGHT_HAVE_PCI for PCI-AHB bridge code

* r7s72100 SoC (RZ/A1H)
  - clks: remove duplicated clock from r7s72100

* R-Car Gen 2: r8a7791 (R-Car M2) and r8a7790 (R-Car H2)
  * Initialize CCF before clock sources
  * Do not setup timer in non-secure mode

* r8a7791 (R-Car M2)
  - Conditionally select MICREL_PHY
  - Add clock index macros for DT sources
  - Add Ether clock

* r8a7790 (R-Car H2)
  - Add clock index macros for DT sources
  - Add I2C support

* r8a7778 (R-Car M1)
  - Add USB Func DMAEngine support
  - camera-rcar header cleanup
  - Add SSIx DMAEngine support

* sh73a0 (SH-Mobile AG5)
  - Add FSI clock support for DT

* tag 'renesas-soc2-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm: shmobile: clks: remove duplicated clock from r7s72100
  ARM: shmobile: koelsch: Conditionally select MICREL_PHY
  ARM: shmobile: rcar-gen2: Initialize CCF before clock sources
  ARM: shmobile: r8a7791: Add clock index macros for DT sources
  ARM: shmobile: r8a7790: Add clock index macros for DT sources
  ARM: shmobile: Add select MIGHT_HAVE_PCI for PCI-AHB bridge code
  ARM: shmobile: r8a7778: add USB Func DMAEngine support
  ARM: rcar-gen2: Do not setup timer in non-secure mode
  ARM: shmobile: r8a7791: add Ether clock
  ARM: shmobile: r8a7778: camera-rcar header cleanup
  ARM: shmobile: sh73a0: add FSI clock support for DT
  ARM: shmobile: r8a7790: add I2C support
  ARM: shmobile: r8a7778: add SSIx DMAEngine support
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'tegra-for-3.14-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc

From Stephen Warren:
ARM: tegra: SoC-specific core code changes

This branch contains various miscellaneous changes to code in the
mach-tegra/ directory. It is baased on v3.13-rc1, and shouldn't conflict
with anything else.

* tag 'tegra-for-3.14-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: tegra: select PINCTRL_TEGRA124 for Tegra124 SoC
  ARM: tegra: use section-sized static mappings for LPAE too
  ARM: tegra: don't hard-code DEBUG_LL baud rate
  ARM: tegra: fix DEBUG_LL combined with LPAE
  ARM: tegra: switch FUSE clock on before usage
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'tegra-for-3.14-powergate' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc

From Stephen Warren:
ARM: tegra: powergate driver changes

This branch includes all the changes to Tegra's powergate driver for 3.14.
These are separate out, since the Tegra DRM changes for 3.14 rely on the
new APIs introduced here.

A few cleanups and fixes are included, plus additions of Tegra124 SoC
support, and a new API for manipulating Tegra's IO rail deep power down
states.

This branch is based on tag tegra-for-3.14-dmas-resets-rework, in order
to avoid conflicts with the addition of common reset controller support
to the powergate driver.

* tag 'tegra-for-3.14-powergate' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: tegra: Add IO rail support
  ARM: tegra: Special-case the 3D clamps on Tegra124
  ARM: tegra: Add Tegra124 powergate support
  ARM: tegra: Export tegra_powergate_remove_clamping()
  ARM: tegra: Export tegra_powergate_power_off()
  ARM: tegra: Rename cpu0 powergate to crail
  ARM: tegra: Fix some whitespace oddities
Signed-off-by: Olof Johansson <olof@lixom.net>

Bringing in the tegra dma/reset rework as a base for new SoC branches.

* tegra/dma-reset-rework: (81 commits)
  spi: tegra: checking for ERR_PTR instead of NULL
  ASoC: tegra: update module reset list for Tegra124
  clk: tegra: remove bogus PCIE_XCLK
  clk: tegra: remove legacy reset APIs
  ARM: tegra: remove legacy DMA entries from DT
  ARM: tegra: remove legacy clock entries from DT
  USB: EHCI: tegra: use reset framework
  Input: tegra-kbc - use reset framework
  serial: tegra: convert to standard DMA DT bindings
  serial: tegra: use reset framework
  spi: tegra: convert to standard DMA DT bindings
  spi: tegra: use reset framework
  staging: nvec: use reset framework
  i2c: tegra: use reset framework
  ASoC: tegra: convert to standard DMA DT bindings
  ASoC: tegra: allocate AHUB FIFO during probe() not startup()
  ASoC: tegra: call pm_runtime APIs around register accesses
  ASoC: tegra: use reset framework
  dma: tegra: register as an OF DMA controller
  dma: tegra: use reset framework
  ...
Signed-off-by: Olof Johansson <olof@lixom.net>

Tested with RIIC2 on a genmai board. Others untested but hopefully
trivial enough to be added.
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>