1. 01 Mar, 2022 3 commits
    • Paolo Bonzini's avatar
      KVM: x86: Do not change ICR on write to APIC_SELF_IPI · d22a81b3
      Paolo Bonzini authored
      Emulating writes to SELF_IPI with a write to ICR has an unwanted side effect:
      the value of ICR in vAPIC page gets changed.  The lists SELF_IPI as write-only,
      with no associated MMIO offset, so any write should have no visible side
      effect in the vAPIC page.
      Reported-by: default avatarChao Gao <chao.gao@intel.com>
      Reviewed-by: default avatarSean Christopherson <seanjc@google.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      d22a81b3
    • Zhenzhong Duan's avatar
      KVM: x86: Fix emulation in writing cr8 · f66af9f2
      Zhenzhong Duan authored
      In emulation of writing to cr8, one of the lowest four bits in TPR[3:0]
      is kept.
      
      According to Intel SDM 10.8.6.1(baremetal scenario):
      "APIC.TPR[bits 7:4] = CR8[bits 3:0], APIC.TPR[bits 3:0] = 0";
      
      and SDM 28.3(use TPR shadow):
      "MOV to CR8. The instruction stores bits 3:0 of its source operand into
      bits 7:4 of VTPR; the remainder of VTPR (bits 3:0 and bits 31:8) are
      cleared.";
      
      and AMD's APM 16.6.4:
      "Task Priority Sub-class (TPS)-Bits 3 : 0. The TPS field indicates the
      current sub-priority to be used when arbitrating lowest-priority messages.
      This field is written with zero when TPR is written using the architectural
      CR8 register.";
      
      so in KVM emulated scenario, clear TPR[3:0] to make a consistent behavior
      as in other scenarios.
      
      This doesn't impact evaluation and delivery of pending virtual interrupts
      because processor does not use the processor-priority sub-class to
      determine which interrupts to delivery and which to inhibit.
      
      Sub-class is used by hardware to arbitrate lowest priority interrupts,
      but KVM just does a round-robin style delivery.
      
      Fixes: b93463aa ("KVM: Accelerated apic support")
      Signed-off-by: default avatarZhenzhong Duan <zhenzhong.duan@intel.com>
      Reviewed-by: default avatarSean Christopherson <seanjc@google.com>
      Message-Id: <20220210094506.20181-1-zhenzhong.duan@intel.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      f66af9f2
    • Paolo Bonzini's avatar
      KVM: x86: flush TLB separately from MMU reset · b5f61c03
      Paolo Bonzini authored
      For both CR0 and CR4, disassociate the TLB flush logic from the
      MMU role logic.  Instead  of relying on kvm_mmu_reset_context() being
      a superset of various TLB flushes (which is not necessarily going to
      be the case in the future), always call it if the role changes
      but also set the various TLB flush requests according to what is
      in the manual.
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      b5f61c03
  2. 25 Feb, 2022 23 commits
  3. 24 Feb, 2022 1 commit
  4. 22 Feb, 2022 4 commits
  5. 18 Feb, 2022 9 commits