- 07 Dec, 2021 6 commits
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Wyatt Wood authored
[Why] When HPD IRQ occurs, it triggers a PSR disable and reenable directly through dc layer. Since it does not pass through the power layer, the layer that tracks whether PSR is enabled or disabled and which masks are set, this layer is now out of sync with the real PSR state in FW. Theoretically PSR can be enabled during hw programming sequences or any other situation where we must disable PSR. [How] Check if PSR is enabled before doing PSR disable/reenable. Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nicholas Kazlauskas authored
[Why] The HW interrupt gets disabled after S3/S4/reset so we don't receive notifications for HPD or AUX from DMUB - leading to timeout and black screen with (or without) DPIA links connected. [How] Re-enable the interrupt after S3/S4/reset like we do for the other DC interrupts. Guard both instances of the outbox interrupt enable or we'll hang during restore on ASIC that don't support it. Fixes: 524a0ba6 ("drm/amd/display: Fix DPIA outbox timeout after GPU reset") Reviewed-by:
Jude Shih <Jude.Shih@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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George Shen authored
[Why] Certain LTTPR require output VS/PE to be explicitly set during PHY test automation. [How] Add vendor-specific sequence to set LTTPR output VS/PE. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
George Shen <George.Shen@amd.com> Signed-off-by:
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George Shen authored
[Why] Some of the vendor-specific workarounds added for transparent mode also need to be applied to non-transparent mode in order to succeed link training consistently. [How] Remove transparent mode check for the required workarounds. Reviewed-by:
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Stanley.Yang authored
skip get ecc info for aldebarn through check ip version do not affect other asic type Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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chen gong authored
145: navi10 IP_VERSION(10, 1, 10) navi12 IP_VERSION(10, 1, 2) navi14 IP_VERSION(10, 1, 1) 92: sienna_cichlid IP_VERSION(10, 3, 0) navy_flounder IP_VERSION(10, 3, 2) vangogh IP_VERSION(10, 3, 1) dimgrey_cavefish IP_VERSION(10, 3, 4) beige_goby IP_VERSION(10, 3, 5) yellow_carp IP_VERSION(10, 3, 3) Signed-off-by:
chen gong <curry.gong@amd.com> Acked-by:
Graham Sider <Graham.Sider@amd.com> Signed-off-by:
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- 02 Dec, 2021 5 commits
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Zhou Qingyang authored
In radeon_driver_open_kms(), radeon_vm_bo_add() is assigned to vm->ib_bo_va and passes and used in radeon_vm_bo_set_addr(). In radeon_vm_bo_set_addr(), there is a dereference of vm->ib_bo_va, which could lead to a NULL pointer dereference on failure of radeon_vm_bo_add(). Fix this bug by adding a check of vm->ib_bo_va. This bug was found by a static analyzer. The analysis employs differential checking to identify inconsistent security operations (e.g., checks or kfrees) between two code paths and confirms that the inconsistent operations are not recovered in the current function or the callers, so they constitute bugs. Note that, as a bug found by static analysis, it can be a false positive or hard to trigger. Multiple researchers have cross-reviewed the bug. Builds with CONFIG_DRM_RADEON=m show no new warnings, and our static analyzer no longer warns about this code. Fixes: cc9e67e3 ("drm/radeon: fix VM IB handling") Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Zhou Qingyang <zhou1615@umn.edu> Signed-off-by:
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Vlad Zahorodnii authored
dm_check_crtc_cursor() doesn't take into account plane transforms when calculating plane scaling, this can result in false positives. For example, if there's an output with resolution 3840x2160 and the output is rotated 90 degrees, CRTC_W and CRTC_H will be 3840 and 2160, respectively, but SRC_W and SRC_H will be 2160 and 3840, respectively. Since the cursor plane usually has a square buffer attached to it, the dm_check_crtc_cursor() will think that there's a scale factor mismatch even though there isn't really. This fixes an issue where kwin fails to use hardware plane transforms. Changes since version 1: - s/orientated/oriented/g Reviewed-by:
Vlad Zahorodnii <vlad.zahorodnii@kde.org> Signed-off-by:
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Zhou Qingyang authored
In amdgpu_connector_lcd_native_mode(), the return value of drm_mode_duplicate() is assigned to mode, and there is a dereference of it in amdgpu_connector_lcd_native_mode(), which will lead to a NULL pointer dereference on failure of drm_mode_duplicate(). Fix this bug add a check of mode. This bug was found by a static analyzer. The analysis employs differential checking to identify inconsistent security operations (e.g., checks or kfrees) between two code paths and confirms that the inconsistent operations are not recovered in the current function or the callers, so they constitute bugs. Note that, as a bug found by static analysis, it can be a false positive or hard to trigger. Multiple researchers have cross-reviewed the bug. Builds with CONFIG_DRM_AMDGPU=m show no new warnings, and our static analyzer no longer warns about this code. Fixes: d38ceaf9 ("drm/amdgpu: add core driver (v4)") Signed-off-by:
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Alex Deucher authored
For SR-IOV, the IP discovery revision number encodes additional information. Handle that case here. v2: drop additional IP versions Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Acked-by:
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Stanley.Yang authored
this is a workaround due to get ecc info failed during gpu recovery [ 700.236122] amdgpu 0000:09:00.0: amdgpu: Failed to export SMU ecc table! [ 700.236128] amdgpu 0000:09:00.0: amdgpu: GPU reset begin! [ 704.331171] amdgpu: qcm fence wait loop timeout expired [ 704.331194] amdgpu: The cp might be in an unrecoverable state due to an unsuccessful queues preemption [ 704.332445] amdgpu 0000:09:00.0: amdgpu: GPU reset begin! [ 704.332448] amdgpu 0000:09:00.0: amdgpu: Bailing on TDR for s_job:ffffffffffffffff, as another already in progress [ 704.332456] amdgpu: Pasid 0x8000 destroy queue 0 failed, ret -62 [ 710.360924] amdgpu 0000:09:00.0: amdgpu: SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x00000013 SMN_C2PMSG_82:0x00000007 [ 710.360964] amdgpu 0000:09:00.0: amdgpu: Failed to disable smu features. [ 710.361002] amdgpu 0000:09:00.0: amdgpu: Fail to disable dpm features! [ 710.361014] [drm:amdgpu_device_ip_suspend_phase2 [amdgpu]] *ERROR* suspend of IP block <smu> failed -62 Signed-off-by:
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- 01 Dec, 2021 29 commits
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Yann Dirson authored
amdgpu_ucode_get_load_type() does not interpret this parameter as documented. It is ignored for many ASIC types (which presumably only support one load_type), and when not ignored it is only used to force direct loading instead of PSP loading. SMU loading is only available for ASICs for which the parameter is ignored. Signed-off-by:
Yann Dirson <ydirson@free.fr> Signed-off-by:
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Philip Yang authored
Refactor userptr and pin_bo path to make it less confusing, move err_pin_bo label up to remove mem from process_info kfd_bo_list. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Philip Yang authored
process_info->lock is used to protect kfd_bo_list, vm_list_head, n_vms and userptr valid/inval list, svm_range_restore_work and svm_range_set_attr don't access those, so do not need to take process_info lock. This will avoid potential circular locking issue. Signed-off-by:
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Graham Sider authored
With device_info initialization being handled in kfd_device_info_init, these structs may be removed. Also add comments to help matching IP versions to asic names. Signed-off-by:
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Graham Sider authored
Initializes kfd->device_info given either asic_type (enum) if GFX version is less than GFX9, or GC IP version if greater. Also takes in vf and the target compiler gfx version. Uses SDMA version to determine num_sdma_queues_per_engine. Convert device_info to a non-pointer member of kfd, change references accordingly. Change unsupported asic condition to only probe f2g, move device_info initialization post-switch. Signed-off-by:
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Graham Sider authored
device_info->asic_name and amdgpu_asic_name[adev->asic_type] both provide asic name strings, with the only difference being casing. Remove asic_name from device_info and replace sysfs entry with lowercase amdgpu_asic_name[]. Ensures string is null-terminated so that this doesn't break if dev->node_props.name ever gets set anywhere else. Signed-off-by:
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shaoyunl authored
This change revert previous commits: 9f4f2c1a ("drm/amd/amdgpu: fix the kfd pre_reset sequence in sriov") 271fd38c ("drm/amdgpu: move kfd post_reset out of reset_sriov function") This change moves the amdgpu_amdkfd_pre_reset to an earlier place in amdgpu_device_reset_sriov, presumably to address the sequence issue that the first patch was originally meant to fix. Some register access(GRBM_GFX_CNTL) only be allowed on full access mode. Move kfd_pre_reset and kfd_post_reset back inside reset_sriov function. Fixes: 9f4f2c1a ("drm/amd/amdgpu: fix the kfd pre_reset sequence in sriov") Fixes: 271fd38c ("drm/amdgpu: move kfd post_reset out of reset_sriov function") Signed-off-by:
shaoyunl <shaoyun.liu@amd.com> Reviewed-by:
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Perry Yuan authored
[Why] IGT bypass test will set crc source as DPRX,and display DM didn`t check connection type, it run the test on the HDMI connector ,then the kernel will be crashed because aux->transfer is set null for HDMI connection. This patch will skip the invalid connection test and fix kernel crash issue. [How] Check the connector type while setting the pipe crc source as DPRX or auto,if the type is not DP or eDP, the crtc crc source will not be set and report error code to IGT test,IGT will show the this subtest as no valid crtc/connector combinations found. 116.779714] [IGT] amd_bypass: starting subtest 8bpc-bypass-mode [ 117.730996] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ 117.731001] #PF: supervisor instruction fetch in kernel mode [ 117.731003] #PF: error_code(0x0010) - not-present page [ 117.731004] PGD 0 P4D 0 [ 117.731006] Oops: 0010 [#1] SMP NOPTI [ 117.731009] CPU: 11 PID: 2428 Comm: amd_bypass Tainted: G OE 5.11.0-34-generic #36~20.04.1-Ubuntu [ 117.731011] Hardware name: AMD CZN/, BIOS AB.FD 09/07/2021 [ 117.731012] RIP: 0010:0x0 [ 117.731015] Code: Unable to access opcode bytes at RIP 0xffffffffffffffd6. [ 117.731016] RSP: 0018:ffffa8d64225bab8 EFLAGS: 00010246 [ 117.731017] RAX: 0000000000000000 RBX: 0000000000000020 RCX: ffffa8d64225bb5e [ 117.731018] RDX: ffff93151d921880 RSI: ffffa8d64225bac8 RDI: ffff931511a1a9d8 [ 117.731022] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 117.731023] CR2: ffffffffffffffd6 CR3: 000000010d5a4000 CR4: 0000000000750ee0 [ 117.731023] PKRU: 55555554 [ 117.731024] Call Trace: [ 117.731027] drm_dp_dpcd_access+0x72/0x110 [drm_kms_helper] [ 117.731036] drm_dp_dpcd_read+0xb7/0xf0 [drm_kms_helper] [ 117.731040] drm_dp_start_crc+0x38/0xb0 [drm_kms_helper] [ 117.731047] amdgpu_dm_crtc_set_crc_source+0x1ae/0x3e0 [amdgpu] [ 117.731149] crtc_crc_open+0x174/0x220 [drm] [ 117.731162] full_proxy_open+0x168/0x1f0 [ 117.731165] ? open_proxy_open+0x100/0x100 BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1546Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Perry Yuan <Perry.Yuan@amd.com> Signed-off-by:
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Philip Yang authored
drm_gem_object_put calls release_notify callback to free the mem structure and unreserve_mem_limit, move it down after the last access of mem and make it conditional call. Signed-off-by:
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Philip Yang authored
To silence the following Smatch static checker warning: drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:2615 svm_range_restore_pages() warn: missing error code here? 'get_task_mm()' failed. 'r' = '0' Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
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Aric Cyr authored
This version brings along the following: - FW promotion to 0.0.95 - DSC fixes for supported Docks - Fixes eDP display issue - Vendor LTTR workarounds - Fixes Tiled display audio issue Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Bhawanpreet.Lakha <Bhawanpreet.Lakha@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Anthony Koo authored
Signed-off-by:
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George Shen authored
[Why] Certain display configurations require an extra delay before reading lane status with certain LTTPR. [How] Add temporary workaround to force AUX RD interval to 16ms for CR and EQ. Needs to be refactored later. Reviewed-by:
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Michael Strauss authored
[WHY] Allow changing DET size with debug flag for testing purposes Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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George Shen authored
[Why] Vendor specific link rate toggle workaround should not be applied outside of link training scenario, such as when outputting PHY test pattern. [How] Add flag to indicate when link training is occuring. Make workaround a no-op when flag is not set. Reviewed-by:
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George Shen authored
[Why] Certain LTTPR require special workarounds in order to comply with DP specifications. [How] Implement vendor specific sequences via DPCD writes to vendor-specific LTTPR registers. Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Mikita Lipski authored
[why] Adding a debugfs to show PSR capability of the panel and the driver. To use: cat /sys/kernel/debug/dri/0/eDP-X/psr_capability Expected output: Sink support: no/yes Driver support: no/yes [how] Adding psr_capability to eDP connectors. Reviewed-by:
Mikita Lipski <mikita.lipski@amd.com> Tested-by:
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Brandon Syu authored
[WHY] Driver use primary eDP link stream as the condition to enable fastboot or not. In dual eDP case, set second screen only, this would cause slave eDP timing to be used on primary one. [HOW] Add a check for unmatched eDP link stream. Reviewed-by:
Brandon Syu <Brandon.Syu@amd.com> Tested-by:
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Jimmy Kizito authored
[Why] Certain USB4 docks do not seem to be able to handle disabling DSC once it has been enabled on an MST stream. This can result in blank displays. [How] As a work around, always enable DSC on docks exhibiting this issue. The flag to indicate the use of DSC for MST streams on a USB4 dock is set during detection of the dock and only cleared when the USB4 dock is disconnected. Reviewed-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Tested-by:
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Evgenii Krasnikov authored
[HOW&WHY] Add function to be used for early eDP power on Reviewed-by:
Evgenii Krasnikov <Evgenii.Krasnikov@amd.com> Tested-by:
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Mustapha Ghaddar authored
[WHY] It seems like after a series of plug/unplugs we end up in a situation where tiled display doesnt support Audio. [HOW] The issue seems to be related to when we check streams changed after an HPD, we should be checking the audio_struct as well to see if any of its values changed. Reviewed-by:
Mustapha Ghaddar <mustapha.ghaddar@amd.com> Tested-by:
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Meenakshikumar Somasundaram authored
[Why] During otg sync trigger, plane states are used to decide whether the otg is already synchronized or not. There are scenarions when otgs are disabled without plane state getting disabled and in such case the otg is excluded from synchronization. [How] Introduced pipe_idx_syncd in pipe_ctx that tracks each otgs master pipe. When a otg is disabled/enabled, pipe_idx_syncd is reset to itself. On sync trigger, pipe_idx_syncd is checked to decide whether a otg is already synchronized and the otg is further included or excluded from synchronization. Reviewed-by:
meenakshikumar somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by:
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Shen, George authored
[Why] VS and PE requested by repeater should not persist for the sink. [How] Clear DPCD lane settings after repeater link training finishes. Reviewed-by:
Wesley Chalmers <wesley.chalmers@amd.com> Acked-by:
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Dale Zhao authored
[Why] Using the hdmi_disable option doesnt disable 6GB bandwidth [How] Add debug.hdmi20_disable flage when checking 6GB enable or not. Reviewed-by:
Chris Park <Chris.Park@amd.com> Reviewed-by:
Dale Zhao <dale.zhao@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] When trying to lightup two 4k60 non-DSC displays behind a branch device that supports DSC we can't lightup both at once due to bandwidth limitations - each requires 48 VCPI slots but we only have 63. [How] The workaround already exists in the code but is guarded by a CONFIG that cannot be set by the user and shouldn't need to be. Check for specific branch device IDs to device whether to enable the workaround for multiple display scenarios. Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Stylon Wang authored
[Why + How] Enable P010 for SDR video applications. Reviewed-by:
Stylon Wang <stylon.wang@amd.com> Tested-by:
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Fangzhi Zuo authored
Change since v1: add brief description 1. Add hdmi frl pcon support to existing asic family. 2. Determine pcon frl capability based on pcon dpcd. 3. pcon frl is taken into consideration into mode validation. v2: squash in warning fix (Alex) Signed-off-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Fangzhi Zuo authored
1. Parse DSC caps from PCON DPCD 2. Policy determins if DSC is decoded at PCON 3. Enable/disable DSC at PCON Signed-off-by:
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Lijo Lazar authored
On aldebaran, RLC also controls GFXCLK. Skip halting RLC during GFX IP suspend and keep it running till PMFW disables all DPMs. [ 578.019986] amdgpu 0000:23:00.0: amdgpu: GPU reset begin! [ 583.245566] amdgpu 0000:23:00.0: amdgpu: Failed to disable smu features. [ 583.245621] amdgpu 0000:23:00.0: amdgpu: Fail to disable dpm features! [ 583.245639] [drm:amdgpu_device_ip_suspend_phase2 [amdgpu]] *ERROR* suspend of IP block <smu> failed -62 [ 583.248504] [drm] free PSP TMR buffer Signed-off-by:Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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