- 04 May, 2014 1 commit
-
-
Maxime Ripard authored
The pins description structure were declared as const, but the of_device_id data magic was losing it silently. Make sure we have it on both sides. And now that we're using const, we can also remove the useless cast in probe. Signed-off-by:Maxime Ripard <maxime.ripard@free-electrons.com>
-
- 24 Apr, 2014 1 commit
-
-
Thomas Petazzoni authored
This commit extends the pinctrl mvebu logic with a new driver to cover Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281 variants of Orion5x, which are the three ones supported by the old style MPP code in arch/arm/mach-orion5x/. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
-
- 23 Apr, 2014 9 commits
-
-
Heiko Stübner authored
In some cases it is nice to be able to simply control a gpio output via the PIN_CONFIG_OUTPUT option without having a driver control it. Thus add support for it to the rockchip pinctrl driver. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
-
Heiko Stübner authored
Till now pinconf_get only set the argument value into the config parameter effectively removing the actual config param value. As other pinctrl drivers do, it might be nicer to keep the config param intact. Therefore construct a real pinconfig value from param and arg in pinconf_get Signed-off-by:
-
Linus Walleij authored
This switches the SiRF pinctrl driver over to using the gpiolib irqchip helpers simplifying some of the code. Signed-off-by:
Barry Song <Baohua.Song@csr.com> Signed-off-by:
-
Barry Song authored
all gpio banks are in one chip, that makes software clean in mapping irq and gpio. Signed-off-by:
-
Linus Walleij authored
The sirfsoc_irqchip_to_bank() is obviously misnamed, as it is not converting an irqchip to a bank but converts a gpiochip to a bank so rename it sirfsoc_gpiochip_to_bank(). Acked-by:
-
Andy Gross authored
Define a new binding for the Qualcomm TLMMv2 based pin controller inside the IPQ8064. Signed-off-by:
Andy Gross <agross@codeaurora.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by:
-
Andy Gross authored
This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the Qualcomm IPQ8064 platform. Signed-off-by:
-
Boris BREZILLON authored
List all sunxi pinctrl compatible strings in order to be able to grep for those values. Signed-off-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by:
-
Tomasz Figa authored
This patch adds driver data (bank list and EINT layout) for Exynos3250 to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output ports. There are 23 general port groups. Changes from v1: - Add signed-off of sender - Post only separated patch for pinctrl from following patchset(v1) : https://lkml.org/lkml/2014/4/10/286 Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Chanwoo Choi <cw00.choi@samsung.com> Acked-by:
Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by:
-
- 22 Apr, 2014 29 commits
-
-
Alexander Stein authored
pin_to_mask expects a bank pin number. So do not add the chip base. Without that patch cat /sys/kernel/debug/gpio looks like that: GPIOs 0-31, platform/fffff200.gpio, fffff200.gpio: [spi32766.0] GPIOfffff200.gpio5: [gpio] set [ads7846_pendown] GPIOfffff200.gpio15: [gpio] set [ohci_vbus] GPIOfffff200.gpio21: [gpio] set [ohci_vbus] GPIOfffff200.gpio24: [gpio] set [button1] GPIOfffff200.gpio28: [gpio] clear [button2] GPIOfffff200.gpio29: [gpio] clear GPIOs 32-63, platform/fffff400.gpio, fffff400.gpio: [sda] GPIOfffff400.gpio4: [periph A] [scl] GPIOfffff400.gpio5: [periph A] [spi32766.3] GPIOfffff400.gpio11: [periph A] [error] GPIOfffff400.gpio22: [periph A] [run] GPIOfffff400.gpio23: [periph A] GPIOs 64-95, platform/fffff600.gpio, fffff600.gpio: [reset_pin] GPIOfffff600.gpio29: [periph A] GPIOs 96-127, platform/fffff800.gpio, fffff800.gpio: [led1] GPIOfffff800.gpio5: [periph A] [led2] GPIOfffff800.gpio6: [periph A] [led3] GPIOfffff800.gpio7: [periph A] [led4] GPIOfffff800.gpio8: [periph A] GPIOs 128-159, platform/fffffa00.gpio, fffffa00.gpio: [button3] GPIOfffffa00.gpio10: [periph A] [button4] GPIOfffffa00.gpio12: [periph A] Note that every bank despite bank 0 only shows "periph A" which are obviously used as GPIOs. Signed-off-by:
Alexander Stein <alexanders83@web.de> Acked-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
-
Alexander Stein authored
This converts the AT91 pin control driver to register its chained irq handler and irqchip using the helpers in the gpiolib core. Signed-off-by:
-
Stephen Warren authored
The kerneldoc for struct tegra_pingroup didn't describe all of the fields in the struct. Add some extra kerneldoc to fix that. Signed-off-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
-
Stephen Warren authored
When an attempt is made to configure an unsupported option on a pin, print the DT property name of that option, so it's easier to debug what the problem is. Signed-off-by:
Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by:
-
Stephen Warren authored
The range of npins and function ID values is small enough to fit into a u8. Use this type rather than unsigned to shrink the pinmux data tables. Signed-off-by:
-
Stephen Warren authored
The fsafe value in the pingroup data tables is only used to implement tegra_pinctrl_disable(). The only reason this function is called is when dynamically switching between pinmux states, i.e. when disabling the old state before programming the new state. It's simpler to have the new target state define the expected value of each pin (and all current DTs do that). This also gives more flexibility, since it allows individual boards explicit control over the "inactive" mux function for each pin, rather than requiring it to be an SoC-specific value. Assuming this, we can get rid of the fsafe value from the driver completely, thus saving some more space in the driver tables. While re-writing the content of tegra124_pingroups[], fix the indentation to use a TAB instead of spaces. Signed-off-by:
-
Stephen Warren authored
Any SoC which supports the einput, odrain, lock, ioreset, or rcv_sel options has the relevant HW register fields in the same register as the mux function selection. Similarly, the drvtype option is always in the drive register, if it is supported at all. Hence, we don't need to have struct *_reg fields in the pin group table to define which register and bank to use for those options. Delete this to save space in the driver's data tables. However, many of those options are not supported on all SoCs, or not supported on some pingroups. We need a way to detect when they are supported. Previously, this was indicated by setting the struct *_reg field to -1. With the struct *_reg fields removed, we use the struct *_bit fields for this purpose instead. The struct *_bit fields need to be expanded from 5 to 6 bits in order to store a value outside the valid HW bit range of 0..31. Even without removing the struct *_reg fields, we still need to add code to validate the struct *_bit fields, since some struct *_bit fields were already being set to -1, without an option-specific struct *_reg field to "guard" them. In other words, before this change, the pinmux driver might allow some unsupported options to be written to HW. Signed-off-by:
-
Wolfram Sang authored
Signed-off-by:
Wolfram Sang <wsa@sang-engineering.com> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
-
Wolfram Sang authored
Add the muxing for the last missing i2c rcar core. Fix the sorting for SH_PFC_PIN_NAMED while we are here. Signed-off-by:
-
Fabio Estevam authored
With debug enabled we get better readability dumps of the mux_mode register if we use hexadecimal format instead: imx6sl-pinctrl 20e0000.iomuxc: MX6SL_PAD_FEC_REF_CLK: 0x10 0x0001b0a8 Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Acked-by:
Shawn Guo <shawn.guo@freescale.com> Signed-off-by:
-
Kuninori Morimoto authored
Reviewed-by:
Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
-
Kuninori Morimoto authored
Reviewed-by:
-
Antoine Ténart authored
According to the MODULE_AUTHOR() comments, the author name should be "Name <email>" or just "Name". Add the missing '>'. Signed-off-by: Antoine TÃ
© nart <antoine.tenart@free-electrons.com> Acked-by: -
Antoine Ténart authored
When using a group only pinctrl driver, which does not have any information on the pins it is useless to define a get_group_pins always returning an empty list of pins. When not using get_group_pin[1], a driver must implement it so pins = NULL and num_pins = 0. This patch makes it the default behaviour if not defined in the pinctrl driver when used in pinmux enable and disable funtions and in pinctrl_groups_show. It also adds a check in pinctrl_get_group_pins and return -EINVAL if not defined. This function is called in the gpiolib when adding when pingroup range. It cannot be used if no group is defined, so this seams reasonable. [1] get_group_pin(struct pinctrl_dev *pctldev, unsigned selector, const unsigned **pins, unsigned *num_pins); Signed-off-by: Antoine TÃ
© nart <antoine.tenart@free-electrons.com> Signed-off-by: -
Boris BREZILLON authored
The A31 SoC has PL and PM banks and thus increase the default ARCH_NR_GPIO. Signed-off-by:
-
Boris BREZILLON authored
The A31 SoC define a reset line for the R_PIO block which needs to be deasserted. Try to retrieve a reset control and deassert if one was found. Signed-off-by:
-
Boris BREZILLON authored
The A31 SoC provides both PL and PM pio bank through the R_PIO block. These pins all support gpio function and can bbe assigned to system peripherals (like TWI, P2WI, JTAG, ...) Signed-off-by:
-
Boris BREZILLON authored
Add support for multiple pin controller instances. First remove the static definition of the sunxi gpio chip struct and fill the dynamically struct instead. Then define a new pin_base field in the sunxi_pinctrl_desc which will be used to specify the gpiochip base pin. Signed-off-by:
-
Boris BREZILLON authored
Define PL and PM pin macros. Signed-off-by:
-
Boris BREZILLON authored
Disable the clk when failing to probe the pin controller device. Signed-off-by:
-
Boris BREZILLON authored
Check the clk_prepare_enable return value to avoid false positive probe. Signed-off-by:
-
Maxime COQUELIN authored
This patch completes the one that used ARRAY_SIZE for STiH407 and STiH416 for setting ninput_delays and noutput_delays fields. Signed-off-by:
Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by:
-
Maxime COQUELIN authored
This patch adds const qualifier where applicable. Reported-by:
Joe Perches <joe@perches.com> Signed-off-by:
-
Axel Lin authored
Define __PINCTRL_LANTIQ_H to prevent multiple inclusion. Signed-off-by:
Axel Lin <axel.lin@ingics.com> Signed-off-by:
-
Axel Lin authored
It's only referenced in this file, make it static. Signed-off-by:
-
Laurent Pinchart authored
The DU parallel interface ODDF signal is optional, move it out of the HSYNC/VSYNC group into a group of its down. The CDE and DISP signals are independent, split them to two different groups. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
-
Uwe Kleine-König authored
This driver is only useful on MSM8x74, so let the driver depend on ARCH_QCOM but allow compile coverage testing. The main benefit is that the driver isn't available to be selected for machines that don't have the matching hardware. Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by:
-
Bjorn Andersson authored
This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the Qualcomm APQ8064 platform. Signed-off-by:
-
Bjorn Andersson authored
DT bindingdocumentation for qcom,apq8064-pinctrl driver. Signed-off-by:
-
