- 06 Jul, 2012 40 commits
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Roland Stigge authored
Via of_get_named_gpio(), wp_gpio can become -EPROBE_DEFER which now makes probe() return -EPROBE_DEFER as well to wait until the gpio controller is probed before trying to probe lpc32xx_slc again. Signed-off-by:
Roland Stigge <stigge@antcom.de> Acked-by:
Alexandre Pereira da Silva <aletes.xgr@gmail.com> Signed-off-by:
Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by:
David Woodhouse <David.Woodhouse@intel.com>
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Roland Stigge authored
This patch makes the lpc32xx_slc driver use of_get_named_gpio() instead of of_get_named_gpio_flags() whose flags are discarded anyway. Signed-off-by:
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Alexandre Pereira da Silva authored
This patch supports missing wp gpio. Signed-off-by:
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Josh Wu authored
The Programmable Multibit ECC (PMECC) controller is a programmable binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. This controller can be used to support both SLC and MLC NAND Flash devices. It supports to generate ECC to correct 2, 4, 8, 12 or 24 bits of error per sector of data. To use PMECC in this driver, the user needs to set the address and size of PMECC, PMECC error location controllers and ROM. And also needs to pass the correction capability, the sector size and ROM lookup table offsets via dt. This driver has been tested on AT91SAM9X5-EK and AT91SAM9N12-EK with JFFS2, YAFFS2, UBIFS and mtd-utils. Signed-off-by:
Hong Xu <hong.xu@atmel.com> Signed-off-by:
Josh Wu <josh.wu@atmel.com> Tested-by:
Richard Genoud <richard.genoud@gmail.com> Acked-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
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Josh Wu authored
Add DT support for PMECC parameters. Signed-off-by:
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Paul Gortmaker authored
The SBC8260 support was dropped back when we moved from ppc to powerpc. We are now also dropping the support for the EOL SBC8560, so we can also delete this mapping support, as they were the only users of it. Artem: also remove the symbol from the Makefile. Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
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Shmulik Ladkani authored
Amend the comment to reflect the fact NAND_BBT_NO_OOB refers to the location of the bad block table marker. Signed-off-by:
Shmulik Ladkani <shmulik.ladkani@gmail.com> Signed-off-by:
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Marek Vasut authored
Signed-off-by:
Marek Vasut <marex@denx.de> Signed-off-by:
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Brian Norris authored
This function only returns 0 or -1, so make that clear. Signed-off-by:
Brian Norris <computersforpeace@gmail.com> Signed-off-by:
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Brian Norris authored
These descriptors are for BBT's that don't use OOB; the "no_bbt" name doesn't really make sense. Signed-off-by:
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Richard Genoud authored
The commit bf4289cb removed the use of CONFIG_MTD_NAND_ATMEL_ECC_NONE and CONFIG_MTD_NAND_ATMEL_ECC_HW but the Kconfig file was forgotten. This patch remove those inoperative options. Signed-off-by:
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Brian Norris authored
This manufacturer ID is used under the name Spansion. Signed-off-by:
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Paul Bolle authored
The Kconfig help on "Flash cmd/query data swapping" still mentions LART_ENDIAN_BYTE. That option used to be relevant for setting CONFIG_MTD_CFI_LART_BIT_SWAP. That option and macro got both removed in v2.4.11-pre4. So, although LART endianness sounds intriguing, that part of the help text can be removed. And, while we're touching this choice, move the help text up one level. Currently it's available under the "NO" option, while it's relevant for all three options. Signed-off-by:
Paul Bolle <pebolle@tiscali.nl> Signed-off-by:
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Chunhe Lan authored
Signed-off-by:
Chunhe Lan <Chunhe.Lan@freescale.com> Signed-off-by:
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Roland Stigge authored
This patch adds support for the SLC NAND controller inside the LPC32xx SoC. [dwmw2: 21st century pedantry] Signed-off-by:
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Josh Wu authored
There is an implemention of hardware ECC write page function which may return an error indication. For instance, using Atmel HW PMECC to write one page into a nand flash, the hardware engine will compute the BCH ecc code for this page. so we need read a the status register to theck whether the ecc code is generated. But we cannot assume the status register always can be ready, for example, incorrect hardware configuration or hardware issue, in such case we need write_page() to return a error code. Since the definition of 'write_page' function in struct nand_ecc_ctrl is 'void'. So this patch will: 1. add return 'int' value for 'write_page' function. 2. to be consitent, add return 'int' value for 'write_page_raw' fuctions too. 3. add code to test the return value, and if negative, indicate an error happend when write page with ECC. 4. fix the compile warning in all impacted nand flash driver. Note: I couldn't compile-test all of these easily, as some had ARCH dependencies. Signed-off-by:
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Josh Wu authored
This patch moves hw ecc initialization code to one function. Signed-off-by:
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Alexandre Pereira da Silva authored
Signed-off-by:
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Alexandre Pereira da Silva authored
Signed-off-by:
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Shmulik Ladkani authored
The code responsible for reading the version of the mirror bbt was incorrectly using the descriptor of the main bbt. Pass the mirror bbt descriptor to 'scan_read_raw' when reading the version of the mirror bbt. Signed-off-by:
Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: stable@vger.kernel.org [v2.6.37+] Signed-off-by:
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Sascha Hauer authored
This adds snippets to the i.MX51/53 devicetrees for the nand flash controller. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Acked-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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Sascha Hauer authored
The only relevant change between i.MX51 and i.MX53 is that a bitfield is shifted one bit to the left. Signed-off-by:
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Sascha Hauer authored
The i.MX v3 nand controller (i.MX5) needs two memory resources. Traditionally we have the AXI resource first. For sorting in this driver into the devicetree it feels much more natural to have the IP resource first. This patch swaps the ordering of these two resources. Signed-off-by:
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Sascha Hauer authored
To make the error path simpler and to make subsequent patches easier. Signed-off-by:
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Scott Wood authored
Previously the remove method was looping and removing all chips, which is obviously not the right thing to do — left over from when the driver was organized differently and that was the remove method for the entire controller. This would result in bad things happening if you have more than one NAND chip, and remove the module. This also fixes priv->dev to properly point to the chip's device rather than the controller's. Until now priv->dev was only used for error/debug prints (and it's an improvement there), so this shouldn't break anything. Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
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ing. Federico Fuga authored
Adds JEDEC ID for the 1.8V version of WinBond w25q32. Signed-off-by:
Federico Fuga <fuga@studiofuga.com> Signed-off-by:
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Fabio Estevam authored
Prepare the clock before enabling it. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
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Brian Norris authored
According to its documentation, the NAND_NO_READRDY option is always used when autoincrement is not supported. Autoincrement support was recently dropped, so we can drop this options as well (defaulting to "no read ready check"). Signed-off-by:
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Brian Norris authored
This option was never used and isn't currently used. Signed-off-by:
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Brian Norris authored
Eon's new NAND flash: EN27LN1G08. Signed-off-by:
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Artem Bityutskiy authored
This is a clean-up patch which removes the own pseudo-random numbers generator from the speed- and stress-tests and makes them use the 'random32()' generator instead. [dwmw2: Merge later fix for negative offsets] Signed-off-by:
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Bastian Hecht authored
In hardware ecc mode, the flctl now writes and reads the oob data provided by the user. Additionally the ECC is now returned in normal page reads, not only when using the explicit NAND_CMD_READOOB command. Signed-off-by:
Bastian Hecht <hechtb@gmail.com> Acked-by:
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Bastian Hecht authored
There are multiple reasons for a rewrite: - a race exists: when _4ECCEND is set, _4ECCFA may become true too meanwhile, which is lost and a non-correctable error is treated as correctable. - the ECC statistics don't get properly propagated to the base code. - empty pages would get marked as corrupted The rewrite resolves the issues and I hope it gives a more explicit code flow structure. Signed-off-by:
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Bastian Hecht authored
When we use hardware ecc, the flctl is run in so-called "sector access mode". We can bundle 4 sector accesses when using 2KiB page sizes to read a whole page at once and speed up things. Signed-off-by:
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Bastian Hecht authored
As the equation mtd->writesize == eccsteps * eccsize holds, we can simplify the code. The second loop of the 1st hunk is never entered, so we delete it. Signed-off-by:
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Bastian Hecht authored
The flctl uses 10 bytes ECC data for every 512 bytes sector. This patch makes the controller write all 40 bytes instead of 10 bytes only. Signed-off-by:
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Bastian Hecht authored
The flctl hardware has changed and a new OOB layout must be adapted for 2KiB page size NAND chips when using hardware ECC. The related bit fields ECCPOS[0-2] are gone — the bits are marked as reserved now in the datasheet. As there are no official users of the hardware ECC so far, they are completely removed. Signed-off-by:
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Bastian Hecht authored
When the data transfer between the controller and the NAND chip fails, we now get notified. Signed-off-by:
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Bastian Hecht authored
Add the unmapping for the error case and for the driver removal. Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Brian Norris authored
This patch is simply an added warning in the comments. Ideally, this patch need not be merged, but rather, a developer will write a proper solution that can use the ecc.read_oob_raw and ecc.write_oob_raw interfaces. Signed-off-by:
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