1. 25 Apr, 2019 3 commits
    • Tomas Winkler's avatar
      mei: hdcp: use own Kconfig file · d65bf042
      Tomas Winkler authored
      The mei/hdcp module have its own Makefile
      so naturally it should have associated Kconfig
      in the same directory.
      Signed-off-by: default avatarTomas Winkler <tomas.winkler@intel.com>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      d65bf042
    • Patrick Venture's avatar
      drivers/misc: Add Aspeed P2A control driver · 01c60dce
      Patrick Venture authored
      The ASPEED AST2400, and AST2500 in some configurations include a
      PCI-to-AHB MMIO bridge.  This bridge allows a server to read and write
      in the BMC's physical address space.  This feature is especially useful
      when using this bridge to send large files to the BMC.
      
      The host may use this to send down a firmware image by staging data at a
      specific memory address, and in a coordinated effort with the BMC's
      software stack and kernel, transmit the bytes.
      
      This driver enables the BMC to unlock the PCI bridge on demand, and
      configure it via ioctl to allow the host to write bytes to an agreed
      upon location.  In the primary use-case, the region to use is known
      apriori on the BMC, and the host requests this information.  Once this
      request is received, the BMC's software stack will enable the bridge and
      the region and then using some software flow control (possibly via IPMI
      packets), copy the bytes down.  Once the process is complete, the BMC
      will disable the bridge and unset any region involved.
      
      The default behavior of this bridge when present is: enabled and all
      regions marked read-write.  This driver will fix the regions to be
      read-only and then disable the bridge entirely.
      
      The memory regions protected are:
       * BMC flash MMIO window
       * System flash MMIO windows
       * SOC IO (peripheral MMIO)
       * DRAM
      
      The DRAM region itself is all of DRAM and cannot be further specified.
      Once the PCI bridge is enabled, the host can read all of DRAM, and if
      the DRAM section is write-enabled, then it can write to all of it.
      Signed-off-by: default avatarPatrick Venture <venture@google.com>
      Reviewed-by: default avatarAndrew Jeffery <andrew@aj.id.au>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      01c60dce
    • Patrick Venture's avatar
      dt-bindings: misc: aspeed-p2a-ctrl: add support · 28703c6e
      Patrick Venture authored
      Document the ast2400, ast2500 PCI-to-AHB bridge control driver bindings.
      Signed-off-by: default avatarPatrick Venture <venture@google.com>
      Reviewed-by: default avatarRob Herring <robh@kernel.org>
      Reviewed-by: default avatarAndrew Jeffery <andrew@aj.id.au>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      28703c6e
  2. 21 Apr, 2019 2 commits
  3. 20 Apr, 2019 11 commits
  4. 19 Apr, 2019 24 commits