- 10 Feb, 2016 40 commits
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Christian König authored
Add a job_alloc_with_ib helper and proper job submission. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Alex Deucher <alexander.deucer@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
There is no point in sending them through the scheduler. Signed-off-by:
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Christian König authored
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Christian König authored
We can't submit to multiple rings at the same time anyway. Signed-off-by:
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Christian König authored
The padding depends on the firmware version and we need that for BO moves as well, not only for VM updates. v2: new approach of making pad_ib a ring function v3: fix typo in macro name Signed-off-by:
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Christian König authored
Don't keep that around twice. Signed-off-by:
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Christian König authored
And use them in the CS instead of allocating IBs and jobs separately. Signed-off-by:
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Christian König authored
Specifying no IBs on command submission is invalid, stop crashing badly when somebody tries it. Signed-off-by:
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Christian König authored
Just a leftover from semaphores. Signed-off-by:
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Christian König authored
Just leftovers from the semaphores. Signed-off-by:
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Christian König authored
Instead of when we try to bind it check the usermm when we try to use it in the IOCTLs. Signed-off-by:
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Matthew Dawson authored
When the radeon driver resets a gpu, it attempts to test whether all the rings can successfully handle an IB. If these rings fail to respond, the process will wait forever. Another gpu reset can't happen at this point, as the current reset holds a lock required to do so. Instead, make all the IB tests run with a timeout, so the system can attempt to recover in this case. While this doesn't fix the underlying issue with card resets failing, it gives the system a higher chance of recovering. These timeouts have been confirmed to help both a Tathi and Hawaii card recover after a gpu reset. This also adds a new function, radeon_fence_wait_timeout, that behaves like fence_wait_timeout. It is used instead of fence_wait_timeout as it continues to work during a reset. radeon_fence_wait is changed to be implemented using this function. V2: - Changed the timeout to 1s, as the default 10s from radeon_wait_timeout was too long. A timeout of 100ms was tested and found to be too short. - Changed radeon_fence_wait_timeout to behave more like fence_wait_timeout. Reviewed-by:
Matthew Dawson <matthew@mjdsystems.ca> Signed-off-by:
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Alex Deucher authored
Drop needless function wrapper. Signed-off-by: -
Christian König authored
Move that out of the main IOCTL function. Signed-off-by:
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Christian König authored
And use it in UVD/VCE command patching. v2: squash in Christian's fix Signed-off-by:
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Christian König authored
We only need a few dw here. Signed-off-by:
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Alex Deucher authored
VBIOS does this for us in asic_init. v2: update iceland as well Reviewed-by:
Monk Liu <monk.liu@amd.com> Reviewed-by:
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Alex Deucher authored
VBIOS does this for us in asic_init. Reviewed-by:
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Alex Deucher authored
Generally a good idea between VM sessions. We need a way to detect VM pass-through in general and always run asic_init in that case. Reviewed-by:
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Alex Deucher authored
Required to make desicions about certain code pathes. Reviewed-by:
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Alex Deucher authored
This table is found on boards that support SR-IOV. This will be used to determine if the board supports SR-IOV and allow the driver to take specific action in certain cases. Reviewed-by:
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Alex Deucher authored
amdgpu_boot_test_post_card() is not used anywhere. Probably a leftover from the original port from radeon. Reviewed-by:
Tom St Denis <tom.stdenis@amd.com> Signed-off-by:
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Maruthi Srinivas Bayyavarapu authored
ACP IP have internal DMA controller, DW I2S controller and DSPs as separate power tiles. DMA and I2S devices are added to generic pm domain, so that entire IP can be powered off/on at appropriate times. Unused DSPs are made to be powered off though they are powered on during ACP pm domain power on sequence. Signed-off-by:
Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> Reviewed-by:
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Maruthi Bayyavarapu authored
This adds the ACP (Audio CoProcessor) IP driver and wires it up to the amdgpu driver. The ACP block provides the DMA engine for i2s based ALSA driver. This is required for audio on APUs that utilize an i2s codec. Reviewed-by:
Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by:
Murali Krishna Vemuri <murali-krishna.vemuri@amd.com> Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Christian König authored
That works with other values as well. Signed-off-by:
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Christian König authored
Don't calculate the end address multiple times. Signed-off-by:
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Christian König authored
Neither the global nor the local mutex exists any more and amdgpu doesn't support cayman. Signed-off-by:
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Christian König authored
No need to fence every page table, just the page directory is enough. Signed-off-by:
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Christian König authored
If we can't copy entries from the GTT or fill them with one command split up the mapping operation into multiple ones. v2: agd: rebase on upstream v3: squash in Christian's fix Signed-off-by:
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Christian König authored
That allows the VM code to use GART BOs from other driver instances. v2: don't use copy optimization for foreign GARTs, that won't work. v3: some more comment cleanups v4: agd: rebase on upstream Signed-off-by:
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Christian König authored
No need to duplicate that code over and over again. Also stop using the flags to determine if we need to map the addresses. v2: constify the pages_addr v3: rebased, fix typo in commit message Signed-off-by:
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Christian König authored
Those are just leftovers from the time we wrote the VM updates directly to the ring. Signed-off-by:
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Christian König authored
Crashing the system doesn't helps at all. Also properly return -EINVAL if size or alignment are outside valid ranges. Signed-off-by:
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Monk Liu authored
since the dependency job is also scheduled by the same scheduler with the job depended on it, no need to call wake up scheduler when the dep is scheduled. Signed-off-by:
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Alex Deucher authored
This adds the DCE8 enum header. Acked-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
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Eric Huang authored
Reviewed-by:
Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by:
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Eric Huang authored
These add the interfaces for manual clock control. Reviewed-by:
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Eric Huang authored
These add the interfaces for manual clock control. Reviewed-by:
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Eric Huang authored
The new sysfs interfaces: pp_num_states: Read-only, return the number of all pp states, 0 if powerplay is not available. pp_cur_state: Read-only, return the index number of current pp state. pp_force_state: Read-write, to write a power state index will switch to selected state forcedly and enable forced state mode, disable forced state mode. such as "echo >...". pp_table: Read-write, binary output, to be used to read or write the dpm table, the maximum file size is 4KB of page size. pp_dpm_sclk: Read-write, reading will return a dpm levels list, to write an index number will force powerplay to set the corresponding dpm level. pp_dpm_mclk: same as sclk. pp_dpm_pcie: same as sclk. And add new setting "manual" to the existing interface power_dpm_force_performance_level. Reviewed-by:
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Christian König authored
With the scheduler enabled we don't need that any more. Signed-off-by:
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