- 07 Jul, 2016 40 commits
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Alex Deucher authored
ATPX dGPU power control requires a 200ms delay between power off and on. This should fix dGPU failures on resume from power off. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Alex Deucher authored
The presence of the power control method should be determined via the presence of the method in function 0. However, some sbioses only set the appropriate bits in function 1 so use then to override a missing power control function. Reviewed-by:
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Alex Deucher authored
Windows 10 (and some 8.1) systems use standardized ACPI calls for hybrid laptops to control dGPU power. Detect those cases and disable the AMD specific ATPX power control. Reviewed-by:
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Alex Deucher authored
Now that we handle this correctly, there is no need to force it. Reviewed-by:
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Alex Deucher authored
On PX systems without dGPU power control, use PCI_D3hot. Reviewed-by:
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Alex Deucher authored
The runtime pm sequence is different depending on whether or not the platform supports ATPX dGPU power control. Reviewed-by:
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Alex Deucher authored
ATPX dGPU power control requires a 200ms delay between power off and on. This should fix dGPU failures on resume from power off. Reviewed-by:
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Alex Deucher authored
The presence of the power control method should be determined via the presence of the method in function 0. However, some sbioses only set the appropriate bits in function 1 so use then to override a missing power control function. Reviewed-by:
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Alex Deucher authored
Windows 10 (and some 8.1) systems use standardized ACPI calls for hybrid laptops to control dGPU power. Detect those cases and disable the AMD specific ATPX power control. Reviewed-by:
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Edmondo Tommasina authored
Reviewed-by:
Edmondo Tommasina <edmondo.tommasina@gmail.com> Signed-off-by:
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Tom St Denis authored
Must wait for SERDES idle before exiting RLC SAFEMODE Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Eric Huang authored
The maximum OD percentage is 20. Reviewed-by:
Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by:
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Eric Huang authored
The maximum OD percentage is 20. Reviewed-by:
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Eric Huang authored
The maximum OD percentage is 20. Reviewed-by:
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Eric Huang authored
The maximum OD percentage is 20. Reviewed-by:
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Eric Huang authored
This implements mclk OverDrive(OD) through sysfs. The new entry pp_mclk_od is read/write. The value of input/output is an integer of the overclocking percentage. Reviewed-by:
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Huang Rui authored
This patch makes powercontainment feature configurable. Currently, the powercontainment is not very stable, so add a module parameter to enable/disable it via user mode. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Christian König authored
Remove the job reference counting and just properly destroy it from a work item which blocks on any potential running timeout handler. Signed-off-by:
Monk.Liu <monk.liu@amd.com> Signed-off-by:
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Christian König authored
Otherwise the locking becomes rather confusing. Signed-off-by:
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Christian König authored
The driver shouldn't mess with the scheduler internals. Signed-off-by:
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Christian König authored
Remembering the code path in a variable to cleanup differently is usually not a good idea at all. Signed-off-by:
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Christian König authored
Ther should be a new line between code and decleration. Also use amdgpu_ib_free() instead of releasing the member manually. Signed-off-by:
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Christian König authored
No need for double housekeeping here. Signed-off-by:
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Christian König authored
Completely pointless and confusing to use a callback to call into the same code file. Signed-off-by:
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Christian König authored
v2: fix even more Signed-off-by:
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Eric Huang authored
Reviewed-by:
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Eric Huang authored
Reviewed-by:
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Eric Huang authored
This extends OD (OverDrive) support to the non-Powerplay code paths. Reviewed-by:
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Eric Huang authored
This extends dpm clock level selection to the non-powerplay code paths. This interface can be used to select individual clock levels. Reviewed-by:
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Tom St Denis authored
Based on Alex's patches this enables GFX PG on CZ. Tested with xonotic-glx/glxgears/supertuxkart and idle desktop. Also read-back registers via umr for verificiation that the bits are truly enabled. Signed-off-by:
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Alex Deucher authored
Fix the logic for enabling/disabling. Signed-off-by: -
Alex Deucher authored
This implements powergating support for CZ/ST asics. Signed-off-by: -
Alex Deucher authored
Add some new GFX powergating flags. Signed-off-by: -
Alex Deucher authored
So they can be shared with other asics. Signed-off-by: -
Alex Deucher authored
This sets up the CP jump table and GDS buffer and sets the PG state registers. Signed-off-by: -
Alex Deucher authored
The size needs to handle the CP JT and GDS. Signed-off-by: -
Alex Deucher authored
The size needs to handle the CP JT and GDS. Signed-off-by: -
Eric Huang authored
This implements sclk overdrive(OD) overclocking support for Polaris10, and the maximum overdrive percentage is 20. Reviewed-by:
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Eric Huang authored
This implements sclk overdrive(OD) overclocking support for Tonga, and the maximum overdrive percentage is 20. Reviewed-by:
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Eric Huang authored
This implements sclk overdrive(OD) overclocking support for Fiji, and the maximum overdrive percentage is 20. Reviewed-by:
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