- 10 Jul, 2018 7 commits
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Junwei Zhang authored
kmap happens after bo pin, so unpin is required on error Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Junwei Zhang authored
Instead of calling gart address space on every bo pin, allocates it on demand v2: fix error handling v3: drop the change on amdgpu_amdkfd_gpuvm.c, not needed. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
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Junwei Zhang authored
It could be got by amdgpu_bo_gpu_offset() if need Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
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git://people.freedesktop.org/~thomash/linuxDave Airlie authored
This introduces a header update and support for multisample surfaces. Signed-off-by:
Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/d020efb8-776d-5e8f-9d9f-122591e074d6@vmware.com
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git://people.freedesktop.org/~thomash/linuxDave Airlie authored
A series of cleanups / reorganizations and modesetting changes that mostly target atomic state validation. [airlied: conflicts with SPDX stuff in amdgpu tree] Signed-off-by:
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
More features for 4.19: - Use core pcie functionality rather than duplicating our own for pcie gens and lanes - Scheduler function naming cleanups - More documentation - Reworked DC/Powerplay interfaces to improve power savings - Initial stutter mode support for RV (power feature) - Vega12 powerplay updates - GFXOFF fixes - Misc fixes Signed-off-by:
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https://github.com/jsarha/linuxDave Airlie authored
tilcdc pull request for v4.19 Single fix to defer probing. Signed-off-by:
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- 06 Jul, 2018 10 commits
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Deepak Rawat authored
A new param DRM_VMW_PARAM_SM4_1, is added for user space to determine availability of SM4.1. Minor version bump for SM4.1. Signed-off-by:
Deepak Rawat <drawat@vmware.com> Reviewed-by:
Sinclair Yeh <syeh@vmware.com> Reviewed-by:
Brian Paul <brianp@vmware.com> Reviewed-by:
Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by:
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Deepak Rawat authored
Support for SVGA3D_SURFACE_MULTISAMPLE and surface mob size according to sample count. Signed-off-by:
Charmaine Lee <charmainel@vmware.com> Signed-off-by:
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Deepak Rawat authored
New ioctls DRM_VMW_GB_SURFACE_CREATE_EXT and DRM_VMW_GB_SURFACE_REF_EXT are added which support 64-bit wide svga device surface flags, quality level and multisample pattern. Signed-off-by:
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Deepak Rawat authored
Since svga device introduced new 64bit SVGA3dSurfaceAllFlags, vmwgfx now stores the surface flags internally as SVGA3dSurfaceAllFlags. For legacy surface define commands, only lower 32-bit is used. Signed-off-by:
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Deepak Rawat authored
SVGA device added new command SVGA3dCmdDefineGBSurface_v3 which allows 64-bit SVGA3dSurfaceAllFlags. This commit adds support for SVGA3dCmdDefineGBSurface_v3 command in vmwgfx. Signed-off-by:
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Deepak Rawat authored
A boolean flag in device private structure to specify if the device support SM4_1. Signed-off-by:
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Neha Bhende authored
A new command to support Intra-Surface-Copy. Signed-off-by:
Neha Bhende <bhenden@vmware.com> Reviewed-by:
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Neha Bhende authored
The device exposes a new capability register. Add support for it. Signed-off-by:
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git://linux-arm.org/linux-ldDave Airlie authored
"mali-dp driver changes for drm-next, includes the driver implementation for writeback, improvements for power management handling in the driver and a debugfs entry for reporting possible internal errors. Please pull at your earliest convenience. Boris Brezillon is also interested in this pull as he is going to change slightly the parameter for the writeback connector's atomic_commit() and he needs to fix the mali-dp driver in his series." Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for 4.19: UAPI Changes: v3d: add fourcc modicfier for fourcc for the Broadcom UIF format (Eric Anholt) Cross-subsystem Changes: console/fbcon: Add support for deferred console takeover (Hans de Goede) Core Changes: dma-fence clean up, improvements and docs (Daniel Vetter) add mask function for crtc, plane, encoder and connector DRM objects(Ville Syrjälä) Driver Changes: pl111: add Nomadik LCDC variant (Linus Walleij) Signed-off-by:
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- 05 Jul, 2018 23 commits
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git://people.freedesktop.org/~thomash/linuxDave Airlie authored
A patchset worked out together with Peter Zijlstra. Ingo is OK with taking it through the DRM tree: This is a small fallout from a work to allow batching WW mutex locks and unlocks. Our Wound-Wait mutexes actually don't use the Wound-Wait algorithm but the Wait-Die algorithm. One could perhaps rename those mutexes tree-wide to "Wait-Die mutexes" or "Deadlock Avoidance mutexes". Another approach suggested here is to implement also the "Wound-Wait" algorithm as a per-WW-class choice, as it has advantages in some cases. See for example http://www.mathcs.emory.edu/~cheung/Courses/554/Syllabus/8-recv+serial/deadlock-compare.html Now Wound-Wait is a preemptive algorithm, and the preemption is implemented using a lazy scheme: If a wounded transaction is about to go to sleep on a contended WW mutex, we return -EDEADLK. That is sufficient for deadlock prevention. Since with WW mutexes we also require the aborted transaction to sleep waiting to lock the WW mutex it was aborted on, this choice also provides a suitable WW mutex to sleep on. If we were to return -EDEADLK on the first WW mutex lock after the transaction was wounded whether the WW mutex was contended or not, the transaction might frequently be restarted without a wait, which is far from optimal. Note also that with the lazy preemption scheme, contrary to Wait-Die there will be no rollbacks on lock contention of locks held by a transaction that has completed its locking sequence. The modeset locks are then changed from Wait-Die to Wound-Wait since the typical locking pattern of those locks very well matches the criterion for a substantial reduction in the number of rollbacks. For reservation objects, the benefit is more unclear at this point and they remain using Wait-Die. Signed-off-by:
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Darren Powell authored
Signed-off-by:
Darren Powell <darren.powell@amd.com> Reviewed-by:
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Sonny Jiang authored
Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Acked-by:
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Mikita Lipski authored
[why] HDMI 2.0 fails to validate 4K@60 timing with 10 bpc [how] Adding a helper function that would verify if the display depth assigned would pass a bandwidth validation. Drop the display depth by one level till calculated pixel clk is lower than maximum TMDS clk. Bugzilla: https://bugs.freedesktop.org/106959Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Tested-by:
Mike Lothian <mike@fireburn.co.uk> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Mikita Lipski authored
[why] HDMI EDID's VSDB contains spectial timings for specifically YCbCr 4:2:0 colour space. In those cases we need to verify if the mode provided is one of the special ones has to use YCbCr 4:2:0 pixel encoding for display info. [how] Verify if the mode is using specific ycbcr420 colour space with the help of DRM helper function and assign the mode to use ycbcr420 pixel encoding. Signed-off-by:
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Darren Powell authored
Eliminating the warnings produced by sphinx when processing the sphinx comments in amdgpu_device.c & amdgpu_mn.c Signed-off-by:
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Gustavo A. R. Silva authored
Add suffix ULL to constant 5 and cast variables target_pix_clk_khz and feedback_divider to uint64_t in order to avoid multiple potential integer overflows and give the compiler complete information about the proper arithmetic to use. Notice that such constant and variables are used in contexts that expect expressions of type uint64_t (64 bits, unsigned). The current casts to uint64_t effectively apply to each expression as a whole, but they do not prevent them from being evaluated using 32-bit arithmetic instead of 64-bit arithmetic. Also, once the expressions are properly evaluated using 64-bit arithmentic, there is no need for the parentheses that enclose them. Addresses-Coverity-ID: 1460245 ("Unintentional integer overflow") Addresses-Coverity-ID: 1460286 ("Unintentional integer overflow") Addresses-Coverity-ID: 1460401 ("Unintentional integer overflow") Fixes: 4562236b ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by:Gustavo A. R. Silva <gustavo@embeddedor.com> Reviewed-by:
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Kees Cook authored
As already done treewide, switch from open-coded multiplication to 2-factor allocation helper. Signed-off-by:
Kees Cook <keescook@chromium.org> Reviewed-by:
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Harry Wentland authored
That change was a merge gone bad. This reverts commit cb1d7eac. Signed-off-by:
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Dan Carpenter authored
The ->info[] array has DAL_IRQ_SOURCES_NUMBER elements so this condition should be >= instead of > or we could read one element beyond the end of the array. Fixes: 4562236b ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
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Rex Zhu authored
delete the same struct define in powerplay, share the struct with display. Acked-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
Set memory clocks same as soc clocks Acked-by:
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Rex Zhu authored
powerplay/dpm export all interfaces in struct amd_pm_funcs. so call common exported interfaces instead of powerplay inner interfaces Also not include header file hwmgr.h Acked-by:
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Rex Zhu authored
Display can notify smu to enable pwe after gpu suspend. It is used in case when display resumes from S3 and wants to start audio driver by enabling pwe Acked-by:
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Alex Deucher authored
These functions duplicated functionality which was ultimately added to the pci core. All users of these functions have been ported to using the newly exposed pci functionality. These functions are no longer used, so drop them. Acked-by:
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Alex Deucher authored
This is the last user of drm_pcie_get_speed_cap_mask. Use the pci version so we can drop drm_pcie_get_speed_cap_mask. Acked-by:
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Alex Deucher authored
Use the newly exported pci functions to get the link width and speed rather than using the drm duplicated versions. Also query the GPU link caps directly rather than hardcoding them. Acked-by:
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Alex Deucher authored
Internal header used by the driver to specify pcie gen speeds of the asic and chipset. Acked-by:
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Alex Deucher authored
So drivers can use them. This can be used to replace duplicate code in the drm subsystem. Acked-by:
Bjorn Helgaas <bhelgaas@google.com> Signed-off-by:
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Alex Deucher authored
Use separate firmware path for amdgpu to avoid conflicts with radeon on SI parts. Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
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Alex Deucher authored
Use separate firmware path for amdgpu to avoid conflicts with radeon on CIK parts. v2: squash in logic simplification (Alex) Reviewed-by:
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Nicolai Hähnle authored
The buffer object backing the user fence is reserved using the non-user fence, i.e., as soon as the non-user fence is signaled, the user fence buffer object can be moved or even destroyed. Therefore, emit the user fence first. Both fences have the same cache invalidation behavior, so this should have no user-visible effect. Signed-off-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by:
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Rex Zhu authored
use smu_helper function smu_set_watermarks_for_clocks_ranges in vega12_set_watermarks_for_clocks_ranges. Reviewed-by:
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