- 12 Jul, 2023 40 commits
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Dmitry Baryshkov authored
Migrate legacy bindings (described in qcom,msm8996-qmp-ufs-phy.yaml) to qcom,sc8280xp-qmp-ufs-phy.yaml. This removes a need to declare the child PHY node or split resource regions. Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230711145153.4167820-2-dmitry.baryshkov@linaro.orgSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Minda Chen authored
Add Starfive JH7110 SoC PCIe 2.0 PHY driver support. PCIe 2.0 PHY default connect to PCIe controller. PCIe PHY can connect to USB 3.0 controller. Signed-off-by:
Minda Chen <minda.chen@starfivetech.com> Reviewed-by:
Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230629075115.11934-5-minda.chen@starfivetech.comSigned-off-by:
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Minda Chen authored
Add Starfive JH7110 SoC USB 2.0 PHY driver support. USB 2.0 PHY default connect to Cadence USB controller. Signed-off-by:
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Minda Chen authored
Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding. PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY. Signed-off-by:
Hal Feng <hal.feng@starfivetech.com> Reviewed-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Minda Chen authored
Add StarFive JH7110 SoC USB 2.0 PHY dt-binding. Signed-off-by:
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Marcin Wierzbicki authored
Add single link SGMII register configuration for no SSC for cdns,sierra-phy-t0 compatibility string. The configuration is based on Sierra Programmer's Guide and validated in Cisco CrayAR SoC. Co-developed-by:
Bartosz Wawrzyniak <bwawrzyn@cisco.com> Signed-off-by:
Marcin Wierzbicki <mawierzb@cisco.com> Link: https://lore.kernel.org/r/20230626105533.2999966-1-mawierzb@cisco.comSigned-off-by:
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Alex Bee authored
This adds a bunch of new pixel clock- and tmds rates to the pre-pll table which are required to get more VESA and some DMT rates working. It has been completely re-calculated to match the min- and max-vco of (750 MHz - 3.2 GHz) requirements. If more than one configuration would have been possible the lowest fbdiv and refdiv (and therefore lowest vco rate) has been preferred. It's important to note, that RK3228 version of the phy does not support fractional dividers. To support the most possible rates for this version also in both 8-bit and 10-bit variant, some rates are not exact. The maximum deviation of the pixel clock is 0.26, which perfectly fits into VESA DMT recommendation of 0.5%. I tested all possible rates on several screens from different manufacturers with both RK3228 and RK3328. Both pre- and post-PLL locking are slighlty faster now. Signed-off-by:
Alex Bee <knaerzche@gmail.com> Signed-off-by:
Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230615171005.2251032-7-jonas@kwiboo.seSigned-off-by:
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Huicong Xu authored
Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and not in pixel clock rate. When the hdmiphy clock is configured with the same pixel clock rate using clk_set_rate() the clock framework do not signal the hdmi phy driver to set_rate when switching between 8-bit and Deep Color. This result in pre/post pll not being re-configured when switching between regular 8-bit and Deep Color video formats. Fix this by calling set_rate in power_on to force pre pll re-configuration. Signed-off-by:
Huicong Xu <xhc@rock-chips.com> Signed-off-by:
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Jonas Karlman authored
inno_write is used to configure 0xaa reg, that also hold the POST_PLL_POWER_DOWN bit. When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not taken into consideration. Fix this by keeping the power down bit until configuration is complete. Also reorder the reg write order for consistency. Fixes: 53706a11 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by:
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Jonas Karlman authored
no_c is not used in any calculation, lets remove it. Signed-off-by:
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Zheng Yang authored
inno_hdmi_phy_rk3328_clk_recalc_rate() is returning a rate not found in the pre pll config table when the fractal divider is used. This can prevent proper power_on because a tmdsclock for the new rate is not found in the pre pll config table. Fix this by saving and returning a rounded pixel rate that exist in the pre pll config table. Fixes: 53706a11 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by:
Zheng Yang <zhengyang@rock-chips.com> Signed-off-by:
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Jonas Karlman authored
inno_hdmi_phy_rk3328_clk_set_rate() is using the RK3228 macro when configuring vco_div_5 on RK3328. Fix this by using correct vco_div_5 macro for RK3328. Fixes: 53706a11 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by:
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Dmitry Baryshkov authored
Extact qmp_combo_configure_dp_clocks(), a common function to setup PHY clocks depending on the selected link rate. Signed-off-by:
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Dmitry Baryshkov authored
The only difference between qmp_v6_dp_aux_init() and qmp_v4_dp_aux_init() is the address of COM_BIAS_EN_CLKBUFLR_EN register. Move it to register layout and drop the duplicate function. Signed-off-by:
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Dmitry Baryshkov authored
The functions qmp_v5_configure_dp_phy() and qmp_v6_configure_dp_phy() are now copies of qmp_v4_configure_dp_phy(). Drop them and use the v4 function in all the cases. Signed-off-by:
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Dmitry Baryshkov authored
Use register layout for TX_HIGHZ_DRVR_EN and TX_TRANSCEIVER_BIAS_EN registers. This will allow us to unify qmp_v[456]_configure_dp_phy() functions in the next commit. Signed-off-by:
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Dmitry Baryshkov authored
Instead of passing additional registers to qmp_combo_configure_dp_swing(), reuse qphy_reg_layout and add those registers to register layout maps. Signed-off-by:
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Dmitry Baryshkov authored
Instead of passing additional registers to qmp_v456_configure_dp_phy(), reuse qphy_reg_layout and add those registers to register layout maps. Signed-off-by:
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Dmitry Baryshkov authored
It seems the commit a2e927b0 ("phy: qcom-qmp-combo: Add sc8280xp USB/DP combo phys") contained a typo for selecting bias0_en values. First, bias0_en and bias1_en are expected to be symmetrical, and then the vendor driver also uses `flipped : 0x3E : 0x15` statement for bias0_en. Correct bias0_en programming to follow this. Fixes: 49742e9e ("phy: qcom-qmp-combo: Add support for SM8550") Fixes: a2e927b0 ("phy: qcom-qmp-combo: Add sc8280xp USB/DP combo phys") Signed-off-by:
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Piyush Mehta authored
Enabling clock for all the lanes consumes power even PHY is active or inactive. To resolve this, enable/disable clocks in phy_init/phy_exit. By default clock is disabled for all the lanes. Whenever phy_init called from USB, SATA, or display driver, etc. It enabled the required clock for requested lane. On phy_exit cycle, it disabled clock for the active PHYs. During the suspend/resume cycle, each USB/ SATA/ display driver called phy_exit/phy_init individually. It disabled clock on exit, and enabled on initialization for the active PHYs. Signed-off-by:
Piyush Mehta <piyush.mehta@amd.com> Link: https://lore.kernel.org/r/20230613140250.3018947-3-piyush.mehta@amd.comSigned-off-by:
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Piyush Mehta authored
Added Runtime power management support to the xilinx phy driver and using DEFINE_RUNTIME_DEV_PM_OPS new macros allows the compiler to remove the unused dev_pm_ops structure and related functions if !CONFIG_PM without the need to mark the functions __maybe_unused. Signed-off-by:
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AngeloGioacchino Del Regno authored
All of the entries do fit in a maximum of 82 columns, which is acceptable. While at it, also remove the useless comma on the last entry and add the usual sentinel comment. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230525115258.90091-4-angelogioacchino.delregno@collabora.comSigned-off-by:
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AngeloGioacchino Del Regno authored
Switch to devm_of_clk_add_hw_provider() in the probe function: this also allows to entirely remove the .remove_new() callback, as its only task was to unregister the clock provider. Signed-off-by:
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AngeloGioacchino Del Regno authored
Instead of registering a struct clk, directly register clk_hw: this allows us to cleanup a pointer to struct clk from struct mtk_mipi_tx. Signed-off-by:
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Dmitry Baryshkov authored
When adding support for some of the platforms (sc7180, sc8180x, sdm845, sm8[1234]50), we added USB PHYs for the combo USB+DP QMP PHYs. Now all such usecases were migrated to use USB+DP Combo driver. To simplify the qcom-qmp-usb PHY driver split the legacy USB+dp_com support into a separate driver. Signed-off-by:
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Dmitry Baryshkov authored
The qcom,msm8996-qmp-usb3-phy.yaml defines bindings for several PHYs which predate USB -> USB+DP migration. Now as sm8150 has been migrated, drop the legacy bindings completely. No device trees use them anymore. Newer USB+DP bindings should use combo bindings from the beginning. Signed-off-by:
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Dmitry Baryshkov authored
SM8150 and SC8180X are close relatives. Reuse sc8180x data to support USB+DP combo PHY on SM8150 platform. Signed-off-by:
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Dmitry Baryshkov authored
Add bindings for sm8150 USB+DP PHY. These bindings follow the older style as this is a quick conversion to simplify further driver cleanup. Acked-by:
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Sebastian Reichel authored
Printing the OF node is not useful, since we get the same information from the device context. Instead print the reg address, that could not be found. Signed-off-by:
Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230522170324.61349-8-sebastian.reichel@collabora.comSigned-off-by:
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Sebastian Reichel authored
Simplify the code by directly getting the match data via device_get_match_data() instead of open coding its functionality. Signed-off-by:
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Sebastian Reichel authored
Simplify phyclk handling by using devm_clk_get_optional_enabled to acquire and enable the optional clock. This also fixes a resource leak in driver remove path and adds proper error handling. Signed-off-by:
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Sebastian Reichel authored
On RK3588 some registers need to be tweaked to support waking up from suspend when a USB device is plugged into a port from a suspended PHY. Without this change USB devices only work when they are plugged at boot time. Apart from that it optimizes settings to avoid devices toggling between fullspeed and highspeed mode. Signed-off-by:
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Sebastian Reichel authored
Add reset handling support, which is needed for proper operation with RK3588. Signed-off-by:
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Sebastian Reichel authored
Add basic support for the USB2 PHY found in the Rockchip RK3588. Co-developed-by:
William Wu <william.wu@rock-chips.com> Signed-off-by:
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Sebastian Reichel authored
Add compatible for the USB2 phy in the Rockchip RK3588 SoC. Reviewed-by:
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Roger Quadros authored
Instead of a 3D matrix use a key:value pair table for link_cmn_vals, xcvr_diag_vals, pcs_cmn_vals, phy_pma_cmn_vals, cmn_vals, tx_ln_vals and rx_ln_vals. This makes it scaleable for multiple reference clocks. Wherever both CDNS and TI use the same settings, reuse the same data. Introduce CLK_ANY and ANY_SSC enums which are used if the setting is independent of clock rate or SSC type. Signed-off-by:
Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20230530143853.26571-3-sjakhade@cadence.comSigned-off-by:
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Swapnil Jakhade authored
Add register sequences for single link USXGMII configuration supporting 156.25MHz reference clock frequency. Signed-off-by:
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Yangtao Li authored
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by:
Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705090126.26854-3-frank.li@vivo.comSigned-off-by:
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Yangtao Li authored
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by:
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Yangtao Li authored
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by:
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