- 23 Apr, 2021 3 commits
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Coiby Xu authored
Use the minimum of the number of descriptors thus we will allocate the minimal ring buffers for kdump. Signed-off-by:
Coiby Xu <coxu@redhat.com> Tested-by:
Dave Switzer <david.switzer@intel.com> Signed-off-by:
Tony Nguyen <anthony.l.nguyen@intel.com>
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Coiby Xu authored
Set the number of the MSI-X vectors to 1. When MSI-X is enabled, it's not allowed to use more TC queue pairs than MSI-X vectors (pf->num_lan_msix) exist. Thus the number of Tx and Rx pairs (vsi->num_queue_pairs) will be equal to the number of MSI-X vectors, i.e., 1. Signed-off-by:
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Aleksandr Loktionov authored
Refactor repeated link state reporting code into a separate helper functions: i40e_set_vf_link_state() i40e_vc_link_speed2mbps(). Add support of VIRTCHNL_VF_CAP_ADV_LINK_SPEED; Signed-off-by:
Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Signed-off-by:
Aleksandr Loktionov <aleksandr.loktionov@intel.com> Tested-by:
Konrad Jankowski <konrad0.jankowski@intel.com> Signed-off-by:
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- 22 Apr, 2021 23 commits
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David S. Miller authored
Mohammad Athari Bin Ismail says: ==================== Enable DWMAC HW descriptor prefetch This patch series to add setting for HW descriptor prefetch for DWMAC version 5.20 onwards. For Intel platform, enable the capability by default. ==================== Signed-off-by:David S. Miller <davem@davemloft.net>
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Mohammad Athari Bin Ismail authored
Enable HW descriptor prefetch by default by setting plat->dma_cfg->dche = true in intel_mgbe_common_data(). Need to be noted that this capability only be supported in DWMAC core version 5.20 onwards. In stmmac, there is a checking to check the core version. If the core version is below 5.20, this capability wouldn`t be configured. Below is the iperf result comparison between HW descriptor prefetch disabled(DCHE=0b) and enabled(DCHE=1b). Tested on Intel Elkhartlake platform with DWMAC Core 5.20. Observed line rate performance improvement with HW descriptor prefetch enabled. DCHE = 0b [ 5] local 169.254.1.162 port 42123 connected to 169.254.244.142 port 5201 [ ID] Interval Transfer Bitrate Total Datagrams [ 5] 0.00-1.00 sec 96.7 MBytes 811 Mbits/sec 70050 [ 5] 1.00-2.00 sec 96.5 MBytes 809 Mbits/sec 69850 [ 5] 2.00-3.00 sec 96.3 MBytes 808 Mbits/sec 69720 [ 5] 3.00-4.00 sec 95.9 MBytes 804 Mbits/sec 69450 [ 5] 4.00-5.00 sec 96.0 MBytes 806 Mbits/sec 69530 [ 5] 5.00-6.00 sec 96.8 MBytes 812 Mbits/sec 70080 [ 5] 6.00-7.00 sec 96.9 MBytes 813 Mbits/sec 70140 [ 5] 7.00-8.00 sec 96.8 MBytes 812 Mbits/sec 70080 [ 5] 8.00-9.00 sec 97.0 MBytes 814 Mbits/sec 70230 [ 5] 9.00-10.00 sec 96.9 MBytes 813 Mbits/sec 70170 - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate Jitter Lost/Total Datagrams [ 5] 0.00-10.00 sec 966 MBytes 810 Mbits/sec 0.000 ms 0/699300 (0%) sender [ 5] 0.00-10.00 sec 966 MBytes 810 Mbits/sec 0.011 ms 0/699265 (0%) receiver DCHE = 1b [ 5] local 169.254.1.162 port 49740 connected to 169.254.244.142 port 5201 [ ID] Interval Transfer Bitrate Total Datagrams [ 5] 0.00-1.00 sec 97.9 MBytes 821 Mbits/sec 70880 [ 5] 1.00-2.00 sec 98.1 MBytes 823 Mbits/sec 71060 [ 5] 2.00-3.00 sec 98.2 MBytes 824 Mbits/sec 71140 [ 5] 3.00-4.00 sec 98.2 MBytes 824 Mbits/sec 71090 [ 5] 4.00-5.00 sec 98.1 MBytes 823 Mbits/sec 71050 [ 5] 5.00-6.00 sec 98.1 MBytes 823 Mbits/sec 71040 [ 5] 6.00-7.00 sec 98.1 MBytes 823 Mbits/sec 71050 [ 5] 7.00-8.00 sec 98.2 MBytes 824 Mbits/sec 71140 [ 5] 8.00-9.00 sec 98.2 MBytes 824 Mbits/sec 71120 [ 5] 9.00-10.00 sec 98.3 MBytes 824 Mbits/sec 71150 - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate Jitter Lost/Total Datagrams [ 5] 0.00-10.00 sec 981 MBytes 823 Mbits/sec 0.000 ms 0/710720 (0%) sender [ 5] 0.00-10.00 sec 981 MBytes 823 Mbits/sec 0.041 ms 0/710650 (0%) receiver Signed-off-by:
Mohammad Athari Bin Ismail <mohammad.athari.ismail@intel.com> Signed-off-by:
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Mohammad Athari Bin Ismail authored
DWMAC Core 5.20 onwards supports HW descriptor prefetching. Additionally, it also depends on platform specific RTL configuration. This capability could be enabled by setting DMA_Mode bit-19 (DCHE). So, to enable this cability, platform must set plat->dma_cfg->dche = true and the DWMAC core version must be 5.20 onwards. Else, this capability wouldn`t be configured Signed-off-by:
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Hans Westgaard Ry authored
Handling comm_channel_event in mlx4_master_comm_channel uses a double loop to determine which slaves have requested work. The search is always started at lowest slave. This leads to unfairness; lower VFs tends to be prioritized over higher VFs. The patch uses find_next_bit to determine which slaves to handle. Fairness is implemented by always starting at the next to the last start. An MPI program has been used to measure improvements. It runs 500 ibv_reg_mr, synchronizes with all other instances and then runs 500 ibv_dereg_mr. The results running 500 processes, time reported is for running 500 calls: ibv_reg_mr: Mod. Org. mlx4_1 403.356ms 424.674ms mlx4_2 403.355ms 424.674ms mlx4_3 403.354ms 424.674ms mlx4_4 403.355ms 424.674ms mlx4_5 403.357ms 424.677ms mlx4_6 403.354ms 424.676ms mlx4_7 403.357ms 424.675ms mlx4_8 403.355ms 424.675ms ibv_dereg_mr: Mod. Org. mlx4_1 116.408ms 142.818ms mlx4_2 116.434ms 142.793ms mlx4_3 116.488ms 143.247ms mlx4_4 116.679ms 143.230ms mlx4_5 112.017ms 107.204ms mlx4_6 112.032ms 107.516ms mlx4_7 112.083ms 184.195ms mlx4_8 115.089ms 190.618ms Suggested-by:Håkon Bugge <haakon.bugge@oracle.com> Signed-off-by:
Hans Westgaard Ry <hans.westgaard.ry@oracle.com> Reviewed-by:
Tariq Toukan <tariqt@nvidia.com> Signed-off-by:
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Hayes Wang authored
When the timeout occurs, we still have to run the following process for releasing patch request. Otherwise, the PHY would keep no link. Therefore, use break to stop the loop of loading firmware and release the patch request rather than return the function directly. Fixes: 4a51b0e8 ("r8152: support PHY firmware for RTL8156 series") Signed-off-by:
Hayes Wang <hayeswang@realtek.com> Signed-off-by:
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git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queueDavid S. Miller authored
Tony Nguyen says: ==================== 100GbE Intel Wired LAN Driver Updates 2021-04-22 This series contains updates to virtchnl header file, ice, and iavf drivers. Vignesh adds support to warn about potentially malicious VFs; those that are overflowing the mailbox for the ice driver. Michal adds support for an allowlist/denylist of VF commands based on supported capabilities for the ice driver. Brett adds support for iavf UDP segmentation offload by adding the capability bit to virtchnl, advertising support in the ice driver, and enabling it in the iavf driver. He also adds a helper function for getting the VF VSI for ice. Colin Ian King removes an unneeded pointer assignment. Qi enables support in the ice driver to support virtchnl requests from the iavf to configure its own RSS input set. This includes adding new capability bits, structures, and commands to virtchnl header file. Haiyue enables configuring RSS flow hash via ethtool to support TCP, UDP and SCTP protocols in iavf. ==================== Signed-off-by: -
Arnd Bergmann authored
There are a few warnings about empty debug macros in this driver: drivers/net/ethernet/neterion/vxge/vxge-main.c: In function 'vxge_probe': drivers/net/ethernet/neterion/vxge/vxge-main.c:4480:76: error: suggest braces around empty body in an 'if' statement [-Werror=empty-body] 4480 | "Failed in enabling SRIOV mode: %d\n", ret); Change them to proper 'do { } while (0)' expressions to make the code a little more robust and avoid the warnings. Signed-off-by:Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Loic Poulain authored
Ensure that the poll system call returns proper error flags when port is removed (nullified port ops), allowing user side to properly fail, without further read or write. Fixes: 9a44c1cc ("net: Add a WWAN subsystem") Signed-off-by:
Loic Poulain <loic.poulain@linaro.org> Reviewed-by:
Leon Romanovsky <leonro@nvidia.com> Signed-off-by:
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Ido Schimmel authored
When the sampling truncation length is invalid (zero), pass the length of the packet. Without the fix, no payload is reported to user space when the truncation length is zero. Fixes: a8700c3d ("netdevsim: Add dummy psample implementation") Signed-off-by:
Ido Schimmel <idosch@nvidia.com> Acked-by:
Jakub Kicinski <kuba@kernel.org> Signed-off-by:
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Arnd Bergmann authored
A link time bug that I had fixed before has come back now that another sub-module was added to the enetc driver: ERROR: modpost: "enetc_ierb_register_pf" [drivers/net/ethernet/freescale/enetc/fsl-enetc.ko] undefined! The problem is that the enetc Makefile is not actually used for the ierb module if that is the only built-in driver in there and everything else is a loadable module. Fix it by always entering the directory this time, regardless of which symbols are configured. This should reliably fix the problem and prevent it from coming back another time. Fixes: 112463dd ("net: dsa: felix: fix link error") Fixes: e7d48e5f ("net: enetc: add a mini driver for the Integrated Endpoint Register Block") Signed-off-by:
Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by:
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Arnd Bergmann authored
The MANA driver causes a build failure in some configurations when it selects an unavailable symbol: WARNING: unmet direct dependencies detected for PCI_HYPERV Depends on [n]: PCI [=y] && X86_64 [=y] && HYPERV [=n] && PCI_MSI [=y] && PCI_MSI_IRQ_DOMAIN [=y] && SYSFS [=y] Selected by [y]: - MICROSOFT_MANA [=y] && NETDEVICES [=y] && ETHERNET [=y] && NET_VENDOR_MICROSOFT [=y] && PCI_MSI [=y] && X86_64 [=y] drivers/pci/controller/pci-hyperv.c: In function 'hv_irq_unmask': drivers/pci/controller/pci-hyperv.c:1217:9: error: implicit declaration of function 'hv_set_msi_entry_from_desc' [-Werror=implicit-function-declaration] 1217 | hv_set_msi_entry_from_desc(¶ms->int_entry.msi_entry, msi_desc); | ^~~~~~~~~~~~~~~~~~~~~~~~~~ A PCI driver should never depend on a particular host bridge implementation in the first place, but if we have this dependency it's better to express it as a 'depends on' rather than 'select'. Signed-off-by:Dexuan Cui <decui@microsoft.com> Signed-off-by:
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Haiyue Wang authored
Provide the ability to enable SCTP RSS hashing by ethtool. It gives users option of generating RSS hash based on the SCTP source and destination ports numbers, IPv4 or IPv6 source and destination addresses. Signed-off-by:
Haiyue Wang <haiyue.wang@intel.com> Tested-by:
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Haiyue Wang authored
Provides the ability to enable UDP RSS hashing by ethtool. It gives users option of generating RSS hash based on the UDP source and destination ports numbers, IPv4 or IPv6 source and destination addresses. Signed-off-by:
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Haiyue Wang authored
Provides the ability to enable TCP RSS hashing by ethtool. It gives users option of generating RSS hash based on the TCP source and destination ports numbers, IPv4 or IPv6 source and destination addresses. Signed-off-by:
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Haiyue Wang authored
Add the virtchnl message interface to VF, so that VF can request RSS input set(s) based on PF's capability. This framework allows ethtool RSS config support on the VF driver. Signed-off-by:
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Qi Zhang authored
Add the handler for virtchnl message VIRTCHNL_OP_DEL_RSS_CFG to remove an existing RSS configuration with matching hashed fields. Signed-off-by:
Vignesh Sridhar <vignesh.sridhar@intel.com> Co-developed-by:
Jia Guo <jia.guo@intel.com> Signed-off-by:
Qi Zhang <qi.z.zhang@intel.com> Signed-off-by:
Bo Chen <BoX.C.Chen@intel.com> Signed-off-by:
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Qi Zhang authored
Currently, RSS hash input is not available to AVF by ethtool, it is set by the PF directly. Add the RSS configure support for AVF through new virtchnl message, and define the capability flag VIRTCHNL_VF_OFFLOAD_ADV_RSS_PF to query this new RSS offload support. Signed-off-by:
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Brett Creeley authored
Currently, the driver gets the VF's VSI by using a long string of dereferences (i.e. vf->pf->vsi[vf->lan_vsi_idx]). If the method to get the VF's VSI were to change the driver would have to change it in every location. Fix this by adding the helper ice_get_vf_vsi(). Signed-off-by:
Brett Creeley <brett.creeley@intel.com> Tested-by:
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Colin Ian King authored
Pointer vsi is being re-assigned a value that is never read, the assignment is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by:Colin Ian King <colin.king@canonical.com> Tested-by:
Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by:
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Brett Creeley authored
Add code to support UDP segmentation offload (USO) for hardware that supports it. Suggested-by:
Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by:
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Brett Creeley authored
As the hardware is capable of supporting UDP segmentation offload, add a capability bit to virtchnl.h to communicate this and have the driver advertise its support. Suggested-by:
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Michal Swiatkowski authored
Declare bitmap of allowed commands on VF. Initialize default opcodes list that should be always supported. Declare array of supported opcodes for each caps used in virtchnl code. Change allowed bitmap by setting or clearing corresponding bit to allowlist (bit set) or denylist (bit clear). Signed-off-by:
Michal Swiatkowski <michal.swiatkowski@intel.com> Tested-by:
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Vignesh Sridhar authored
Attempt to detect malicious VFs and, if suspected, log the information but keep going to allow the user to take any desired actions. Potentially malicious VFs are identified by checking if the VFs are transmitting too many messages via the PF-VF mailbox which could cause an overflow of this channel resulting in denial of service. This is done by creating a snapshot or static capture of the mailbox buffer which can be traversed and in which the messages sent by VFs are tracked. Co-developed-by:
Yashaswini Raghuram Prathivadi Bhayankaram <yashaswini.raghuram.prathivadi.bhayankaram@intel.com> Signed-off-by:
Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> Signed-off-by:
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- 21 Apr, 2021 14 commits
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Marek Behún authored
This causes error reported by kernel test robot. Signed-off-by:
Marek Behún <kabel@kernel.org> Fixes: 41d26bf4 ("net: phy: marvell: refactor HWMON OOP style") Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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Vladimir Oltean authored
When CONFIG_NET_SWITCHDEV is disabled, the shim for switchdev_port_attr_set inside br_mc_disabled_update returns -EOPNOTSUPP. This is not caught, and propagated to the caller of br_multicast_add_port, preventing ports from joining the bridge. Reported-by:
Christian Borntraeger <borntraeger@de.ibm.com> Fixes: ae1ea84b ("net: bridge: propagate error code and extack from br_mc_disabled_update") Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Tested-by:
Nikolay Aleksandrov <nikolay@nvidia.com> Signed-off-by:
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Adam Ford authored
The call to clk_disable_unprepare() can happen before priv is initialized. This means moving clk_disable_unprepare out of out_release into a new label. Fixes: 8ef7adc6 ("net: ethernet: ravb: Enable optional refclk") Signed-off-by:
Adam Ford <aford173@gmail.com> Reviewed-by:
Sergei Shtylyov <sergei.shtylyov@gmail.com> Signed-off-by:
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Ong Boon Leong authored
TSO and TBS cannot coexist, for now we set Intel mGbE controller to use below TX Queue mapping: TxQ0 uses TSO and the rest of TXQs supports TBS. Signed-off-by:
Ong Boon Leong <boon.leong.ong@intel.com> Signed-off-by:
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Oleksij Rempel authored
Starting with patch: a8b659e7 ("net: dsa: act as passthrough for bridge port flags") drivers without "port_bridge_flags" callback will fail to join the bridge. Looking at the code, -EOPNOTSUPP seems to be the proper return value, which makes at least microchip and atheros switches work again. Fixes: 5961d6a1 ("net: dsa: inherit the actual bridge port flags at join time") Signed-off-by:
Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by:
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Dan Carpenter authored
We recently added some new locking to this function but one error path was overlooked. We need to drop the lock before returning. Fixes: f4da5652 ("net: stmmac: Add support for external trigger timestamping") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Wong Vee Khee <vee.khee.wong@linux.intel.com> Signed-off-by:
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David S. Miller authored
Tobias Waldekranz says: ==================== net: dsa: mv88e6xxx: Tiny fixes/improvements Just some small things I have noticed that do not fit in any other series. ==================== Signed-off-by: -
Tobias Waldekranz authored
Export the raw PVT data in a devlink region so that it can be inspected from userspace and compared to the current bridge configuration. Signed-off-by:
Tobias Waldekranz <tobias@waldekranz.com> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
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Tobias Waldekranz authored
In the unlikely event of the VTU being loaded to the brim with 4k entries, the last one was placed in the buffer, but the size reported to devlink was off-by-one. Make sure that the final entry is available to the caller. Fixes: ca4d632a ("net: dsa: mv88e6xxx: Export VTU as devlink region") Signed-off-by:
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Tobias Waldekranz authored
Because ADRR is not a thing. Signed-off-by:
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David S. Miller authored
Srujana Challa says: ==================== Add support for CN10K CPT block OcteonTX3 (CN10K) silicon is a Marvell next-gen silicon. CN10K CPT introduces new features like reassembly support and some feature enhancements. This patchset adds new mailbox messages and some minor changes to existing mailbox messages to support CN10K CPT. v1-v2 Fixed sparse warnings. ==================== Signed-off-by: -
Srujana Challa authored
Adds a new mailbox to get CPT stats, includes performance counters, CPT engines status and RXC status. Signed-off-by:
Narayana Prasad Raju Atherya <pathreya@marvell.com> Signed-off-by:
Srujana Challa <schalla@marvell.com> Signed-off-by:
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Srujana Challa authored
CN10K CPT coprocessor includes a component named RXC which is responsible for reassembly of inner IP packets. RXC has the feature to evict oldest entries based on age/threshold. This patch adds a new mailbox to configure reassembly age or threshold. Signed-off-by:
Jerin Jacob Kollanukkaran <jerinj@marvell.com> Signed-off-by:
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Srujana Challa authored
Adds changes to existing CPT mailbox messages to support CN10K CPT block. This patch also adds new register defines for CN10K CPT. Signed-off-by:
Vidya Sagar Velumuri <vvelumuri@marvell.com> Signed-off-by:
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