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  1. 21 Jun, 2017 1 commit
  3. 14 Feb, 2017 1 commit
    • Hauke Mehrtens's avatar
      spi: lantiq-ssc: add support for Lantiq SSC SPI controller · 17f84b79
      Hauke Mehrtens authored 
      This driver supports the Lantiq SSC SPI controller in master
mode. This controller is found on Intel (former Lantiq) SoCs like
the Danube, Falcon, xRX200, xRX300.

The hardware uses two hardware FIFOs one for received and one for
transferred bytes. When the driver writes data into the transmit FIFO
the complete word is taken from the FIFO into a shift register. The
data from this shift register is then written to the wire. This driver
uses the interrupts signaling the status of the FIFOs and not the shift
register. It is also possible to use the interrupts for the shift
register, but they will send a signal after every word. When using the
interrupts for the shift register we get a signal when the last word is
written into the shift register and not when it is written to the wire.
After all FIFOs are empty the driver busy waits till the hardware is
not busy any more and returns the transfer status.
Signed-off-by: default avatarDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: default avatarHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      17f84b79
  5. 08 Dec, 2016 1 commit
  7. 22 Nov, 2016 1 commit
  9. 24 Sep, 2016 1 commit
  11. 14 Sep, 2016 2 commits
  13. 19 Aug, 2016 1 commit
  15. 08 Aug, 2016 1 commit
    • Rich Felker's avatar
      spi: add driver for J-Core SPI controller · 2cb1b3b3
      Rich Felker authored 
      The J-Core "spi2" device is a PIO-based SPI master controller. It
differs from "bitbang" devices in that that it's clocked in hardware
rather than via soft clock modulation over gpio, and performs
byte-at-a-time transfers between the cpu and SPI controller.

This driver will be extended to support future versions of the J-Core
SPI controller with DMA transfers when they become available.
Signed-off-by: default avatarRich Felker <dalias@libc.org>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      2cb1b3b3
  17. 24 Jul, 2016 1 commit
  19. 18 Apr, 2016 1 commit
  21. 04 Apr, 2016 1 commit
  23. 24 Feb, 2016 1 commit
  25. 05 Feb, 2016 1 commit
    • Lars-Peter Clausen's avatar
      spi: Add Analog Devices AXI SPI Engine controller support · b1353d1c
      Lars-Peter Clausen authored 
      This patch adds support for the AXI SPI Engine controller which is a FPGA
soft-peripheral which is used in some of Analog Devices' reference designs.

The AXI SPI Engine controller is part of the SPI Engine framework[1] and
allows memory mapped access to the SPI Engine control bus. This allows it
to be used as a general purpose software driven SPI controller. The SPI
Engine in addition offers some optional advanced acceleration and
offloading capabilities, which are not part of this patch though and will
be introduced separately.

At the core of the SPI Engine framework is a small sort of co-processor
that accepts a command stream and turns the commands into low-level SPI
transactions. Communication is done through three memory mapped FIFOs in
the register map of the AXI SPI Engine peripheral. One FIFO for the command
stream and one each for transmit and receive data.

The driver translates a spi_message in a command stream and writes it to
the peripheral which executes it asynchronously. This allows it to perform
very precise timings which are required for some SPI slave devices to
achieve maximum performance (e.g. analog-to-digital and digital-to-analog
converters). The execution flow is synchronized to the host system by a
special synchronize instruction which generates a interrupt.

[1] https://wiki.analog.com/resources/fpga/peripherals/spi_engineSigned-off-by: default avatarLars-Peter Clausen <lars@metafoo.de>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      b1353d1c
  27. 15 Jan, 2016 1 commit
  29. 12 Dec, 2015 1 commit
  31. 07 Oct, 2015 1 commit
  33. 28 Aug, 2015 1 commit
  35. 07 Aug, 2015 1 commit
  37. 12 Jun, 2015 1 commit
  39. 09 Jun, 2015 1 commit
  41. 18 Apr, 2015 1 commit
  43. 22 Dec, 2014 2 commits
  45. 24 Nov, 2014 1 commit
    • Beniamino Galvani's avatar
      spi: meson: Add support for Amlogic Meson SPIFC · c3e4bc54
      Beniamino Galvani authored 
      This is a driver for the Amlogic Meson SPIFC (SPI flash controller),
which is one of the two SPI controllers available on the SoC. It
doesn't support DMA and has a 64-byte unified transmit/receive buffer.

The device is optimized for interfacing with SPI NOR memories and
allows the execution of standard operations such as read, page
program, sector erase, etc. in a simplified way, toggling a bit in a
dedicated register. The driver doesn't use those predefined commands
and relies only on custom transfers.
Signed-off-by: default avatarBeniamino Galvani <b.galvani@gmail.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      c3e4bc54
  47. 17 Nov, 2014 1 commit
  49. 19 Aug, 2014 1 commit
    • Rafał Miłecki's avatar
      spi: bcm53xx: driver for SPI controller on Broadcom bcma SoC · 0fc6a323
      Rafał Miłecki authored 
      Broadcom 53xx ARM SoCs use bcma bus that contains various cores (AKA
devices). If board has a serial flash, it's connected over SPI and the
bcma bus includes a SPI controller. Example log from such a board:
bus0: Found chip with id 53010, rev 0x00 and package 0x02
(...)
bus0: Core 18 found: SPI flash controller (manuf 0x4BF, id 0x50A, rev 0x01, class 0x0)

This patch adds a bcma driver for SPI core, it registers SPI master
controller and "bcm53xxspiflash" SPI device.
Signed-off-by: default avatarRafał Miłecki <zajec5@gmail.com>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
      0fc6a323
  51. 04 Jul, 2014 1 commit
    • addy ke's avatar
      spi/rockchip: add driver for Rockchip RK3xxx SoCs integrated SPI · 64e36824
      addy ke authored 
      In order to facilitate understanding, rockchip SPI controller IP design
looks similar in its registers to designware. But IC implementation
is different from designware, So we need a dedicated driver for Rockchip
RK3XXX SoCs integrated SPI. The main differences:

- dma request line: rockchip SPI controller have two DMA request line
  for tx and rx.

- Register offset:
                  RK3288        dw
  SPI_CTRLR0      0x0000        0x0000
  SPI_CTRLR1      0x0004        0x0004
  SPI_SSIENR      0x0008        0x0008
  SPI_MWCR        NONE          0x000c
  SPI_SER         0x000c        0x0010
  SPI_BAUDR       0x0010        0x0014
  SPI_TXFTLR      0x0014        0x0018
  SPI_RXFTLR      0x0018        0x001c
  SPI_TXFLR       0x001c        0x0020
  SPI_RXFLR       0x0020        0x0024
  SPI_SR          0x0024        0x0028
  SPI_IPR         0x0028        NONE
  SPI_IMR         0x002c        0x002c
  SPI_ISR         0x0030        0x0030
  SPI_RISR        0x0034        0x0034
  SPI_TXOICR      NONE          0x0038
  SPI_RXOICR      NONE          0x003c
  SPI_RXUICR      NONE          0x0040
  SPI_MSTICR      NONE          0x0044
  SPI_ICR         0x0038        0x0048
  SPI_DMACR       0x003c        0x004c
  SPI_DMATDLR     0x0040        0x0050
  SPI_DMARDLR     0x0044        0x0054
  SPI_TXDR        0x0400        NONE
  SPI_RXDR        0x0800        NONE
  SPI_IDR         NONE          0x0058
  SPI_VERSION     NONE          0x005c
  SPI_DR          NONE          0x0060

- register configuration:
  such as SPI_CTRLRO in rockchip SPI controller:
    cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
        | (CR0_SSD_ONE << CR0_SSD_OFFSET);
    cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
    cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
    cr0 |= (rs->tmode << CR0_XFM_OFFSET);
    cr0 |= (rs->type << CR0_FRF_OFFSET);
  For more information, see RK3288 chip manual.

- Wait for idle: Must ensure that the FIFO data has been sent out
  before the next transfer.
Signed-off-by: default avataraddy ke <addy.ke@rock-chips.com>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
      64e36824
  53. 14 Apr, 2014 2 commits
  55. 18 Mar, 2014 1 commit
  57. 13 Mar, 2014 1 commit
  59. 23 Feb, 2014 1 commit
    • Maxime Ripard's avatar
      spi: sunxi: Add Allwinner A10 SPI controller driver · b5f65179
      Maxime Ripard authored 
      The older Allwinner SoCs (A10, A13, A10s and A20) all have the same SPI
controller.

Unfortunately, this SPI controller, even though quite similar, is significantly
different from the recently supported A31 SPI controller (different registers
offset, split/merged registers, etc.). Supporting both controllers in a single
driver would be unreasonable, hence the addition of a new driver.

Like its more recent counterpart, it supports DMA, but the driver only does PIO
until we have a dmaengine driver for this platform.
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
      b5f65179
  61. 19 Feb, 2014 1 commit
    • Ivan T. Ivanov's avatar
      spi: Add Qualcomm QUP SPI controller support · 64ff247a
      Ivan T. Ivanov authored 
      Qualcomm Universal Peripheral (QUP) core is an AHB slave that
provides a common data path (an output FIFO and an input FIFO)
for serial peripheral interface (SPI) mini-core. SPI in master
mode supports up to 50MHz, up to four chip selects, programmable
data path from 4 bits to 32 bits and numerous protocol variants.

Cc: Alok Chauhan <alokc@codeaurora.org>
Cc: Gilad Avidov <gavidov@codeaurora.org>
Cc: Kiran Gunda <kgunda@codeaurora.org>
Cc: Sagar Dharia <sdharia@codeaurora.org>
Cc: dsneddon@codeaurora.org
Signed-off-by: default avatarIvan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
      64ff247a
  63. 05 Feb, 2014 1 commit
  65. 04 Dec, 2013 1 commit
  67. 22 Aug, 2013 2 commits
    • Sourav Poddar's avatar
      spi/qspi: Add qspi flash controller · 505a1495
      Sourav Poddar authored 
      The patch add basic support for the quad spi controller.

QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.

The patch will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).

Test details:
-------------
Tested this on dra7 board.
Test1: Ran mtd_stesstest for 40000 iterations.
   - All iterations went through without failure.
Test2: Use mtd utilities:
  - flash_erase to erase the flash device
  - mtd_debug read to read data back.
  - mtd_debug write to write to the data flash.
 diff between the write and read data shows zero.

Acked-by: Felipe Balbi<balbi@ti.com>
Reviewed-by: Felipe Balbi<balbi@ti.com>
Signed-off-by: default avatarSourav Poddar <sourav.poddar@ti.com>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
      505a1495
    • Chao Fu's avatar
      spi:Add Freescale DSPI driver for Vybrid VF610 platform · 349ad66c
      Chao Fu authored 
      The serial peripheral interface (SPI) module implemented on Freescale Vybrid
platform provides a synchronous serial bus for communication between Vybrid
and the external peripheral device.
The SPI supports full-duplex, three-wire synchronous transfer, has TX/RX FIFO
with depth of four entries.

This driver is the SPI master mode driver and has been tested on Vybrid
VF610TWR board.
Signed-off-by: default avatarAlison Wang <b18965@freescale.com>
Signed-off-by: default avatarChao Fu  <b44548@freescale.com>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
      349ad66c
  69. 09 Aug, 2013 1 commit
  71. 15 Jul, 2013 1 commit
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