- 23 Aug, 2017 40 commits
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Abhishek Sahu authored
Add the compatible string for IPQ8074 QPIC NAND controller version 1.5.0 which uses BAM DMA and its FLASH_DEV_CMD registers starting offset is 0x7000. Reviewed-by:
Archit Taneja <architt@codeaurora.org> Signed-off-by:
Abhishek Sahu <absahu@codeaurora.org> Signed-off-by:
Boris Brezillon <boris.brezillon@free-electrons.com>
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Abhishek Sahu authored
Add the compatible string for IPQ4019 QPIC NAND controller version 1.4.0 which uses BAM DMA. Reviewed-by:
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Abhishek Sahu authored
Qualcom IPQ8074 SoC uses QPIC NAND controller version 1.5.0 which uses BAM DMA Engine. Signed-off-by:
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Abhishek Sahu authored
1. Qualcom IPQ4019 SoC uses QPIC NAND controller version 1.4.0 which uses BAM DMA Engine while IPQ806x uses EBI2 NAND which uses ADM DMA Engine. 2. QPIC NAND will 3 BAM channels: command, data tx and data rx while EBI2 NAND uses only single ADM channel. 3. CRCI is only required for ADM DMA and its not required for BAM DMA. Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Abhishek Sahu authored
1. Correct the compatible string for IPQ806x 2. Change the NAND controller and NAND chip nodes name for more clarity. Acked-by:
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Abhishek Sahu authored
The FLASH_DEV_CMD registers starting offset is not same in different QPIC NAND controller versions. This patch adds the starting offset in NAND controller properties and uses the same for calculating the actual offset of these registers. Reviewed-by:
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Abhishek Sahu authored
1. Add the data descriptor preparation function which will be used only by BAM DMA for forming the data SGL’s 2. Add clear BAM transaction and call it before every new request 3. Check DMA mode for ADM or BAM and call the appropriate descriptor formation function. Reviewed-by:
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Abhishek Sahu authored
1. DM_EN is only required for EBI2 NAND controller which uses ADM 2. BAM mode will be disabled after power on reset which needs to be enabled before starting any BAM transfers. Reviewed-by:
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Abhishek Sahu authored
The NAND controller returns ECC failure during read of completely erased codeword. The NAND controller has hardware functionality to detect erased codeword in case of BCH ECC algorithm. The NAND_ERASED_CW_DETECT_CFG register controls the erased codeword/page detection controller. This register should be reset before every page read by setting and clearing bit 0 of NAND_ERASED_CW_DETECT_CFG. Reviewed-by:
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Abhishek Sahu authored
In EBI2, all codeword data will be read in FLASH_BUF_ACC buffer and ADM will copy the data from source (FLASH_BUF_ACC) to destination (memory for data read). In QPIC, there is no FLASH_BUF_ACC and all the codeword data will held in QPIC BAM FIFO buffers. It provides multiple READ_LOCATION registers which will be used for copying the data from FIFO to memory. The READ_LOCATION register will be used to read a specific amount of data from a specific offset within the flash buffer. It supports sequential offset requests. Each request is composed of the following fields: a. Offset within the flash buffer from which data should be read b. Amount of data to be read c. Flag bit specifying the last read request from the flash buffer. Following the last read request the NANDc refers to the buffer as empty. Reviewed-by:
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Abhishek Sahu authored
The QPIC NAND BAM has multiple flags to control the transfer. This patch adds flags parameter in register and data transfer DMA helper functions and modifies all these functions call with appropriate flags using following rule 1. Read and write can’t go in single command descriptor so separate SGL should be used. 2. For some of the requests, NWD flag should be set in BAM DMA descriptor. 3. For Data write, the BAM has internal buffer for each codeword. All write request will modify the data in internal buffer and this buffer will be flushed to NAND device once EOT flag is set. So for all the write requests in single codeword, the EOT should be cleared for all tx data descriptors except the last one. Reviewed-by:
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Abhishek Sahu authored
1. prepare_bam_async_desc is the function which will call all the DMA API’s. It will fetch the outstanding scatter gather list for passed channel and will do the DMA descriptor formation. The DMA flag is dependent upon the type of channel. 2. For ADM DMA, the descriptor is being formed for every DMA request so its sgl count will be always 1 while in BAM DMA, the clubbing of descriptor is being done to increase throughput. 3. ADM DMA uses only one channel while in BAM DMA, data descriptors will be submitted to tx channel (for write) or rx channel (for read) and all the registers read/write descriptors in command channel. Reviewed-by:
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Abhishek Sahu authored
- The BAM transaction is the core data structure which will be used for all the data transfers in QPIC NAND. Since the core framework in nand_base.c is serializing all the NAND requests so allocating BAM transaction before every transfer will be overhead. The memory for it be allocated during probe time and before every transfer, it will be cleared. - The BAM transaction contains the array of command and data scatter gather list and indexes. For every transfer, all the resource will be taken from BAM transaction. - The size of the buffer used for BAM transactions is calculated based on the NAND device with the maximum page size, among all the devices connected to the controller. Reviewed-by:
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Abhishek Sahu authored
The EBI2 NAND controller directly remaps register read buffer with dma_map_sg and DMA address of this buffer will be passed to DMA API’s. While, on QPIC NAND controller, which uses BAM DMA, we read the controller registers by preparing a BAM command descriptor. This command descriptor requires the - controller register address - the DMA address in which we want to store the value read back from the controller register. This command descriptor will be remapped with dma_map_sg and its DMA address will be passed to DMA API’s. Therefore, it's required that we also map our register read buffer for DMA (using dma_map_single). We use the returned DMA address for preparing entries in our command descriptor. This patch adds the DMA mapping support for register read buffer. This buffer will be DMA mapped during allocation time. Before starting of any operation, this buffer will be synced for device operation and after operation completion, it will be synced again for CPU. Reviewed-by: -
Abhishek Sahu authored
1. QPIC NAND controller uses 3 BAM channels: command, data tx and data rx while EBI2 NAND controller uses only single ADM channel. 2. CRCI is only required for ADM DMA and it's not required for BAM DMA. Reviewed-by:
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Abhishek Sahu authored
The current driver only supports EBI2 NAND controller which uses ADM DMA. The latest QCOM SoC uses QPIC NAND controller with BAM DMA. NAND registers and programming sequence are same for EBI2 and QPIC NAND so the same driver can support QPIC NAND also by adding the BAM DMA support. This patch adds the is_bam in NAND property which will be checked for determining the DMA engine type. Reviewed-by:
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Abhishek Sahu authored
Currently driver data is being assigned directly with ECC modes. Now, the plan is to add more NAND controller versions which will have different properties. This patch reorganizes the current driver data assignment by creating NAND controller properties structure which will contain all properties specific to NAND controller. Reviewed-by:
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Abhishek Sahu authored
The NAND page read fails without complete boot chain since NAND_DEV_CMD_VLD value is not proper. The default power on reset value for this register is 0xe - ERASE_START_VALID | WRITE_START_VALID | READ_STOP_VALID The READ_START_VALID should be enabled for sending PAGE_READ command. READ_STOP_VALID should be cleared since normal NAND page read does not require READ_STOP command. Fixes: c76b78d8 ("mtd: nand: Qualcomm NAND controller driver") Cc: stable@vger.kernel.org Reviewed-by: -
Gustavo A. R. Silva authored
platform_get_irq() returns an error code, but the mtk_ecc driver ignores it and always returns -EINVAL. This is not correct and, prevents -EPROBE_DEFER from being propagated properly. Print and propagate the return value of platform_get_irq on failure. This issue was detected with the help of Coccinelle. Signed-off-by:
Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by:
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Gustavo A. R. Silva authored
platform_get_irq() returns an error code, but the sh_flctl driver ignores it and always returns -ENXIO. This is not correct and, prevents -EPROBE_DEFER from being propagated properly. Print and propagate the return value of platform_get_irq on failure. This issue was detected with the help of Coccinelle. Signed-off-by:
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Pan Bian authored
The return value of dma_map_single() should be checked by dma_mapping_error(). However, in function flctl_dma_fifo0_transfer(), its return value is checked against NULL, which could result in failures. Signed-off-by:
Pan Bian <bianpan2016@163.com> Signed-off-by:
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Sergei Shtylyov authored
of_irq_get() may return 0 as well as negative error number on failure, while the driver only checks for the negative values. The driver would then call devm_request_irq() for IRQ0 in its probe method and never get a valid interrupt. Check for 'nc->irq <= 0' instead and return -ENXIO from the driver's probe if of_irq_get() returned 0. Fixes: f88fc122 ("mtd: nand: Cleanup/rework the atmel_nand driver") Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by:
Wenyou Yang <Wenyou.yang@microchip.com> Signed-off-by:
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Martin Blumenstingl authored
According to the datasheet of the H27UCG8T2BTR the NAND Technology field (6th byte of the "Device Identifier Description", bits 0-2) the following values are possible: - 0x0 = 48nm - 0x1 = 41nm - 0x2 = 32nm - 0x3 = 26nm - 0x4 = 20nm - (all others are reserved) Fix this by extending the mask for this field to allow detecting value 0x4 (20nm) as valid NAND technology. Without this the detection of the ECC requirements fails, because the code assumes that the device is a 48nm device (0x4 & 0x3 = 0x0) and aborts with "Invalid ECC requirements" because it cannot map the "ECC Level". Extending the mask makes the ECC requirement detection code recognize this chip as <= 26nm and sets up the ECC step size and ECC strength correctly. Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Fixes: 78f3482d ("mtd: nand: hynix: Rework NAND ID decoding to extract more information") Cc: <stable@vger.kernel.org> Signed-off-by:
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Boris Brezillon authored
Commit a894cf6c ("mtd: nand: mxc: switch to mtd_ooblayout_ops") introduced a bug in the OOB layout description. Even if the driver claims that 3 ECC bytes are reserved to protect 512 bytes of data, it's actually 5 ECC bytes to protect 512+6 bytes of data (some OOB bytes are also protected using extra ECC bytes). Fix the mxc_v1_ooblayout_{free,ecc}() functions to reflect this behavior. Signed-off-by:
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Philipp Zabel authored
Commit a53e35db ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Richard Weinberger <richard@nod.at> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: linux-mtd@lists.infradead.org Signed-off-by:
Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by:
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Arvind Yadav authored
- clk_prepare_enable() can fail here and we must check its return value. - stfsm_probe() can fail here and we must disable clock. Signed-off-by:
Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by:
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Arvind Yadav authored
clk_prepare_enable() can fail here and we must check its return value. Signed-off-by:
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Arvind Yadav authored
clk_prepare_enable() can fail here and we must check its return value. Signed-off-by:
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Arvind Yadav authored
- clk_prepare_enable() can fail here and we must check its return value. - oxnas_nand_probe() can fail here and we must disable clock. Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
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Arvind Yadav authored
clk_prepare_enable() can fail here and we must check its return value. Signed-off-by:
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Arnd Bergmann authored
orion_nand_read_buf uses an inline assembly with the "ldrd" instruction, which is only available from ARMv5 upwards. This used to be fine, since all users have an ARMv5 or ARMv7 CPU, but now we can also build a multiplatform kernel with ARMv4 support enabled in addition to the "kirkwood" (mvebu) platform. This provides an alternative to call the readsl() function that is supposed to have the same effect and is also optimized for performance. I first posted a version of this patch back in 2014, and there was some discussion about it then. This fixes the bugs identified back then and should be a reasonable alternative for the rare corner case. Link: https://patchwork.kernel.org/patch/4144791/ Cc: Jingoo Han <jg1.han@samsung.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Gregory CLEMENT authored
The controller supported by the pxa3xx_nand driver is also available on the mvebu 64-bit SoCs, such as the Armada 7K and Armada 8K SoCs. This patch updates the Kconfig dependency to allow building the kernel for this SoC family too. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
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Abhishek Sahu authored
The NAND controller can support multiple NAND devices having different page sizes. Future code will require us to allocate memory based on the maximum number of codewords among all the devices. We reorganize the NAND device probing such that the ONFI parameters are first read for each connected device to identify the maximum number of codewords possible, and only then proceed with MTD device registration (i.e, call nand_scan_tail and mtd_device_register). This is a reorganization of the existing code and will not change any functionality. Signed-off-by:
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Abhishek Sahu authored
The memset in clear_read_regs is overhead. All the register data will be filled by DMA during NAND operation so making these register variables zero is not required. Signed-off-by:
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Abhishek Sahu authored
Each NAND page consist of multiple codewords. Following is sequence for NAND page write according to hardware guide. 1. Program Power-up configuration, page row, page column address and flash configuration registers. 2. Write NAND_FLASH_CMD followed by NANC_EXEC_CMD for each codeword. 3. Read NAND_FLASH_STATUS for each codeword. The step 1 should be done once for each page and step 2,3 should be done for each codeword. Currently, all the 3 steps are being done for each codeword which is wrong. Now this patch reorganizes page write functions to configure page specific register once and per codeword specific registers for each NAND ECC step. Signed-off-by:
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Abhishek Sahu authored
Each NAND page consist of multiple codewords. Following is sequence for NAND page read according to hardware guide. 1. Program Power-up configuration, page row, page column address and flash configuration registers. 2. Write NAND_FLASH_CMD followed by NANC_EXEC_CMD for each codeword. 3. Read NAND_FLASH_STATUS for each codeword. The step 1 should be done once for each page and step 2,3 should be done for each codeword. Currently, all the 3 steps are being done for each codeword which is wrong. Now this patch reorganizes read page functions to configure page specific register once and per codeword specific registers for each NAND ECC step. Signed-off-by:
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Abhishek Sahu authored
Currently the compatible “qcom,nandcs” is being used for each connected NAND device to support for multiple NAND devices in the same bus. The same thing can be achieved by looking reg property for each sub nodes which contains the chip select number so this patch removes the use of “qcom,nandcs” for specifying NAND device sub nodes. Since there is no user for this driver currently in so changing compatible string is safe. Signed-off-by:
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Abhishek Sahu authored
Currently the compatible “qcom,nandcs” is being used for each connected NAND device to support for multiple NAND devices in the same bus. The same thing can be achieved by looking reg property for each sub nodes which contains the chip select number so this patch removes the use of “qcom,nandcs” for specifying NAND device sub nodes. Since there is no user for this driver currently in so changing compatible string is safe. Signed-off-by:
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Abhishek Sahu authored
The configuration for BCH is not correct in the current driver. The ECC_CFG_ECC_DISABLE bit defines whether to enable or disable the BCH ECC in which 0x1 : BCH_DISABLED 0x0 : BCH_ENABLED But currently host->bch_enabled is being assigned to BCH_DISABLED. Fixes: c76b78d8 ("mtd: nand: Qualcomm NAND controller driver") Cc: stable@vger.kernel.org Signed-off-by:
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Fabio Estevam authored
pinctrl_pm_select_default_state() is already the default pinctrl state and since pinctrl_pm_select_sleep_state() is not used in this driver, there is no need to explicitly call pinctrl_pm_select_default_state(). Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
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