- 15 Dec, 2017 5 commits
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Andrey Grodzovsky authored
Add new parameter to control GPU recovery procedure. v2: Add auto logic where reset is disabled for bare metal and enabled for SR-IOV. Allow forced reset from debugfs. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Roger He authored
include ttm_bo_move_memcpy and ttm_bo_move_ttm Signed-off-by:
Roger He <Hongbo.He@amd.com> Reviewed-by:
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Roger He authored
allow eviction of BOs reserved by the caller when they are not part of the current working set. Reviewed-by:
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Roger He authored
enable eviction of other per VM BOs during allocation and allows reaping of deleted BOs during CS. Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
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Roger He authored
allow_reserved_eviction: Allow eviction of reserved BOs resv: Reservation object to allow reserved evictions with Reviewed-by:
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- 14 Dec, 2017 35 commits
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Chunming Zhou authored
v2: remove SUBPTB member v3: remove last_level, use AMDGPU_VM_PTB directly instead. Signed-off-by:
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Tony Cheng authored
Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Harry Wentland authored
Signed-off-by:
Jordan Lazare <Jordan.Lazare@amd.com> Acked-by:
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Harry Wentland authored
Signed-off-by:
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Harry Wentland authored
We already check this a couple lines earlier. Signed-off-by:
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Yue Hin Lau authored
Signed-off-by:
Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Yongqiang Sun authored
It may take over 200ms for wait hpd ready. To optimize the resume time, we can power on eDP in init_hw, wait for hpd ready when doing link training. also create separate eDP enable function to make sure eDP is powered up before doing and DPCD access, as HPD low will result in DPDC transaction failure. After optimization, setpowerstate 145ms -> 9.8ms, DPMS 387ms -> 18.9ms Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Signed-off-by:
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Eric Yang authored
Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
Andrew Jiang <Andrew.Jiang@amd.com> Acked-by:
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Eric Bernstein authored
Move OPP initialization of mpc tree parameters to hw_init function. Signed-off-by:
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Eric Bernstein authored
Use REG_UPDATE instead of REG_SET for programming MPC out mux. Signed-off-by:
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Vitaly Prosyak authored
When convert from fixed31_32 to other fixed point format use math operation round instead of floor. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Yue Hin Lau authored
Signed-off-by:
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Vitaly Prosyak authored
Also handle fixpoint y values for CM curves Signed-off-by:
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Yue Hin Lau authored
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Dmytro Laktyushkin authored
This reverts commit 978482d0de86 Revert noisy assert messages Signed-off-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Harry Wentland authored
This has proven helpful on other OSes to give a quick state of the DC driver when a bug is reported. Signed-off-by:
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Tony Cheng authored
REG_UPDATE_2 return the reg value it write out through MMIO we need to do a REG_READ to confirm the value is written out Signed-off-by:
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Harry Wentland authored
This code can sometimes look troubling but we trust it as it comes from HW teams with a guarantee of correctness. Add a note to these files to explain this. v2: thing -> things Signed-off-by:
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Harry Wentland authored
In code provided by HW teams we do a NaN check on floats by comparing the number against itself. This confuses most people including myself. Macro it out to make it self-explanatory. Don't do a NaN check for int. v2: parantheses around 'number' expression Signed-off-by:
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Tony Cheng authored
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Tony Cheng authored
This prevents an issue where the MPCC will not go to idle due to us not waiting for it to become idle during disable plane. Signed-off-by:
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Andrew Jiang authored
- Only update DPP clock if it's a full update. - Program viewport on position change. This caused SLS regressions. Signed-off-by:
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Yongqiang Sun authored
When programming cursor position after front end programmed, if position is already set previously, it doesn't make sense to program position with all 0. Cache position and use the parameter after front end programming. Signed-off-by:
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Yongqiang Sun authored
Cursor is abnormal after pipe_ctx is changed in context. Cause: cursor attributes is programmed right after front end programming, but it use old pipe_ctx to program which is not updated yet. Solution: Program cursor regs after context swapped. Signed-off-by:
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Yongqiang Sun authored
Fixed fliped landscape and fliped portrait hard hang. Signed-off-by:
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Eric Murphy-Zaremba authored
Signed-off-by:
Eric Murphy-Zaremba <Eric.Murphy-zaremba@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Eric Bernstein authored
Create opp_set_test_pattern function with similar interface and implementation as timing generator test pattern. Signed-off-by:
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Vitaly Prosyak authored
Add color module to diagnostic compilation Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Eric Bernstein authored
During HW initialization, instead of assuming or detecting the existing MPCC mux configuration and then removing existing planes, reset all the MPCC muxes. Signed-off-by:
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Yue Hin Lau authored
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Yongqiang Sun authored
HDR display playing video underflow is observed when switching to full screen due to program a lower watermark right after unlock otg. Instead of disable plane in next flip coming, if there is a plane disconnected, after otg unlock wait for mpcc idle and disable the plane, then program watermark. So there is enough warter mark to make sure current frame data pass through. Signed-off-by:
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Tony Cheng authored
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