- 15 Apr, 2024 2 commits
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Andy Shevchenko authored
There is no need to allocate chip_data and then validate number of CS pins as it will have the same effect. Hence move number of CS pins validation out of condition in setup(). Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20240403171550.1074644-2-andriy.shevchenko@linux.intel.comSigned-off-by:
Mark Brown <broonie@kernel.org>
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Krzysztof Kozlowski authored
The ID table already has respective entry and MODULE_DEVICE_TABLE and creates proper alias for platform driver. Having another MODULE_ALIAS causes the alias to be duplicated. Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20240414154859.126931-1-krzk@kernel.orgSigned-off-by:
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- 11 Apr, 2024 1 commit
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Lukas Bulwahn authored
Commit 8167bd1c ("ASoC: dt-bindings: ti,pcm1681: Convert to dtschema") converts ti,pcm1681.txt to ti,pcm1681.yaml, but misses to adjust the file entry in TEXAS INSTRUMENTS AUDIO (ASoC/HDA) DRIVERS. Hence, ./scripts/get_maintainer.pl --self-test=patterns complains about a broken reference. Adjust the file entry in TEXAS INSTRUMENTS AUDIO (ASoC/HDA) DRIVERS after this conversion. Signed-off-by:
Lukas Bulwahn <lukas.bulwahn@redhat.com> Link: https://msgid.link/r/20240411075803.53657-1-lukas.bulwahn@redhat.comSigned-off-by:
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- 10 Apr, 2024 5 commits
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Mark Brown authored
Merge series from Théo Lebrun <theo.lebrun@bootlin.com>: This series prepares support for the embedded Cadence Quad SPI controller on Mobileye EyeQ5.
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Théo Lebrun authored
Make cdns,fifo-depth devicetree property optional. Value can be detected at runtime. Upper SRAMPARTITION register bits are read-only. Procedure to find FIFO depth is therefore to write 0xFFFFFFFF and read back to get amount of writeable bits. Signed-off-by:
Théo Lebrun <theo.lebrun@bootlin.com> Link: https://msgid.link/r/20240410-cdns-qspi-mbly-v3-3-7b7053449cf7@bootlin.comSigned-off-by:
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Théo Lebrun authored
Add Mobileye EyeQ5 compatible. Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Théo Lebrun authored
Compatibles are ordered by date of addition. Switch to (deterministic) alphabetical ordering. Reviewed-by:
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Kousik Sanagavarapu authored
Refactor code for "is the node's child available?" check by using the corresponding macro instead, which reads more clearly. While at it, use scope-based cleanup instead of manual of_node_put() calls when getting platform data through cdns_xspi_of_get_plat_data(). This removes the unnecessary "node_child" declaration out of the loop's scope and auto cleans up "node_child" when it goes out of scope, even when we return early due to error. Signed-off-by:
Kousik Sanagavarapu <five231003@gmail.com> Link: https://msgid.link/r/20240410130205.179069-1-five231003@gmail.comSigned-off-by:
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- 08 Apr, 2024 3 commits
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Théo Lebrun authored
cqspi_enable_dtr() is called for each operation, commands or not, reads or writes. It writes CQSPI_REG_CONFIG then waits for idle (three successful reads). Skip that in the no-DTR case if DTR is already disabled. It cannot be skipped in the DTR case as cqspi_setup_opcode_ext() writes to a register and we must wait for idle state. According to ftrace, the average cqspi_exec_mem_op() call goes from 85.4µs to 83.6µs when reading 235M over UBIFS on an octal flash. Signed-off-by:
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Théo Lebrun authored
Avoid of_device_get_match_data() call on each IRQ and each read operation. Store pointer in `struct cqspi_st` device instance. End-to-end performance measurements improve with this patch. On a given octal flash, reading 235M over UBIFS is ~3.4% faster. During that read, the average cqspi_exec_mem_op() call goes from 85.4µs to 80.7µs according to ftrace. The worst case goes from 622.4µs to 615.2µs. Signed-off-by:
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Théo Lebrun authored
The Cadence QSPI Controller driver is used on Mobileye EyeQ5 platform. Allow building on MIPS. Signed-off-by:
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- 02 Apr, 2024 2 commits
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Andy Shevchenko authored
pxa_ssp_request() implies a reference counting, hence the pxa_ssp_free() must be called when we are done. Add missed call. Fixes: bb77c99e ("spi: pxa2xx: Skip SSP initialization if it's done elsewhere") Signed-off-by:
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Krzysztof Kozlowski authored
Core in spi_register_driver() already sets the .owner, so driver does not need to. Signed-off-by:
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- 29 Mar, 2024 3 commits
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Randy Dunlap authored
kernel-doc complains about last_cs_index_mask not described, so add its description. spi.h:778: warning: Function parameter or struct member 'last_cs_index_mask' not described in 'spi_controller' Fixes: 4d8ff6b0 ("spi: Add multi-cs memories support in SPI core") Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Reviewed-by:
Andy Shevchenko <andy@kernel.org> Link: https://lore.kernel.org/r/20240328223340.17159-1-rdunlap@infradead.orgSigned-off-by:
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Mark Brown authored
Merge series from David Lechner <dlechner@baylibre.com>: I found a couple more controller drivers that were checking if the tx_buf and rx_buf fields in the spi_transfer structure were set by a peripheral driver that I missed in [1]. These checks can be removed as well. [1]: https://lore.kernel.org/linux-spi/20240325-spi-remove-is_dma_mapped-v2-1-d08d62b61f1c@baylibre.com/
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Mark Brown authored
Merge series from Louis Chauvet <louis.chauvet@bootlin.com>: This series adds the support for the omap-mcspi multi mode which allows sending SPI messages with a shorter delay between CS and the message. One drawback of the multi-mode is that the CS is raised between each word, so it can only be used with messages containing 1 word transfers and asking for cs_change. Few devices, like FPGAs, may easily workaround this limitation. The first patch removes the current implementation, which is working, but don't comply with what is asked in the spi transfer (The CS is raised by the hardware regardless of cs_change state). No drivers or board file use this implementation upstream. The second patch adds the implementation of the multi-mode, which complies with what is asked in the SPI message. The third patch is the suggested optimization for using MULTI mode in more situations.
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- 28 Mar, 2024 12 commits
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David Lechner authored
There are no more peripheral drivers that set t->tx_dma or t->rx_dma. Therefore, is_dma_mapped is always false and can be removed. Signed-off-by:
David Lechner <dlechner@baylibre.com> Link: https://msgid.link/r/20240328-spi-more-tx-rx-buf-cleanup-v1-2-9ec1ceedf08c@baylibre.comSigned-off-by:
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David Lechner authored
There are no more peripheral drivers that set t->tx_dma or t->rx_dma so these will always == 0. Therefore, we can remove these checks since they are always true. Signed-off-by:
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Andy Shevchenko authored
If SSP has been enumerated elsewhere, skip its initialization in pxa2xx_spi_init_pdata(). Signed-off-by:
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Andy Shevchenko authored
Refactor pxa2xx_spi_init_pdata() by extracting a new pxa2xx_spi_init_ssp() helper which makes code less twisted. It will be easier to continue refactoring for a new coming modification. Signed-off-by:
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Andy Shevchenko authored
Drop rather useless use of ACPI_PTR() and of_match_ptr(). It also removes the necessity to be dependent of.h inclusion. Signed-off-by:
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Andy Shevchenko authored
The PCI || ACPI dependency is the historical part of the x86 support. Narrow the Kconfig option visibility by limiting this dependency to x86. The drop of x86 for PCI case had happened in the commit 2b49ebda ("spi/pxa2xx: allow building on a 64-bit kernel"), while the ACPI was specifically added for Intel Lynx Point in the commit a3496855 ("spi/pxa2xx: add support for Lynxpoint SPI controllers"). Note that X86 covers both 32- and 64-bit variants. Suggested-by:
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Louis Chauvet authored
Enable multimode when a transfer of multiple small words can be transformed in a transfer with a single bigger word. This is allowed as long as the result on the cable is the same, so word_delay must be zero. Signed-off-by:
Louis Chauvet <louis.chauvet@bootlin.com> Link: https://msgid.link/r/20240327-spi-omap2-mcspi-multi-mode-v3-3-c4ac329dd5a2@bootlin.comSigned-off-by:
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Louis Chauvet authored
Introduce support for MULTI-mode in the OMAP2 MCSPI driver. Currently, the driver always uses SINGLE mode to handle the chip select (CS). With this enhancement, MULTI-mode is enabled for specific messages, allowing for a shorter delay between CS enable and the message (some FPGA devices are sensitive to this delay). The OMAP2 MCSPI device can use two different mode to send messages, SINGLE and MULTI: In SINGLE mode, the controller only leverages one single FIFO, and the host system has to manually select the CS it wants to enable. In MULTI mode, each CS is bound to a FIFO, the host system then writes the data to the relevant FIFO, as the hardware will take care of the CS The drawback of multi-mode is that it's not possible to keep the CS enabled between each words. Therefore, this patch enables multi-mode only for specific messages: the spi_message must contain only spi_transfer of 1 word (of any size) with cs_change enabled. A new member is introduced in the omap2_mcspi structure to keep track of the current used mode. Signed-off-by:
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Louis Chauvet authored
Commit 5cbc7ca9 ("spi: spi-omap2-mcspi.c: Toggle CS after each word") introduced the toggling of CS after each word for the omap2-mcspi controller. The implementation is not respectful of the actual spi_message content, so the CS can be raised after each word even if the transfer structure asks to keep the CS active for the whole operation. As it is not used anyway in the current Linux tree, it can be safely removed. Signed-off-by:
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Krzysztof Kozlowski authored
Core in platform_driver_register() already sets the .owner, so driver does not need to. Signed-off-by:
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Krzysztof Kozlowski authored
Core in platform_driver_register() already sets the .owner, so driver does not need to. Signed-off-by:
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Krzysztof Kozlowski authored
Core in spi_register_driver() already sets the .owner, so driver does not need to. Signed-off-by:
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- 26 Mar, 2024 4 commits
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Andy Shevchenko authored
Switch to use dev_err_probe() to simplify the error path and unify a message template. Signed-off-by:
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Andy Shevchenko authored
Keep the PXA*_SSP types together in enum pxa_ssp_type for better maintenance. Signed-off-by:
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Mark Brown authored
Merge series from Andy Shevchenko <andriy.shevchenko@linux.intel.com>: Fix kernel documentation and inclusion block, and dropping the size of the num_chipselect.
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Mark Brown authored
Merge series from Andy Shevchenko <andriy.shevchenko@linux.intel.com>: A couple of cleanups against linux/spi/pxa2xx_spi.h. I'm sending this as v3 to land in the SPI subsystem. Meanwhile I'm preparing an update to make linux/spi/pxa2xx_spi.h private to the subsystem (PXA2xx driver). But the second part will be presented later on (likely after v6.9-rc1). That said, this can be routed either via SoC tree or SPI, up to respective maintainers.
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- 25 Mar, 2024 8 commits
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David Lechner authored
There are no more users of the deprecated is_dma_mapped in struct spi_message so it can be removed. References in documentation and comments are also removed. A few similar checks if xfer->tx_dma or xfer->rx_dma are not NULL are also removed since these are now guaranteed to be NULL because they were previously set only if is_dma_mapped was true. Signed-off-by:
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Raju Rangoju authored
Add support to the SPI controller driver to use SPI MEM framework. SPI subsystem utilizing the SPI memory operations allows to re-use SPI controller drivers for both SPI NOR devices, regular SPI devices as well as SPI NAND devices. Add below functions of spi_mem_ops to support SPI MEM framework - exec-op(): to execute the memory operations. - supports_op(): to check if the memory operation is supported. - adjust_op_size(): to split data transfers so that they don’t exceed the max transfer size supported by the controller. Suggested-by:
Sudheesh Mavila <sudheesh.mavila@amd.com> Co-developed-by:
Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by:
Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by:
Raju Rangoju <Raju.Rangoju@amd.com> Link: https://msgid.link/r/20240229134544.3461757-1-Raju.Rangoju@amd.comSigned-off-by:
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Andy Shevchenko authored
No in-kernel users of struct rspi_plat_data. If required, the software nodes should be used for such users. For now just get rid of it. Signed-off-by:
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Fei Shao authored
All the spi_transfer variables in this file use the name "xfer" except the one in mtk_spi_interrupt(). Align the naming for consistency and easier searching. While at it, reformat one memcpy() usage since the coding style allows 100 column lines today. This commit has no functional change. Signed-off-by:
Fei Shao <fshao@chromium.org> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://msgid.link/r/20240321070942.1587146-3-fshao@chromium.orgSigned-off-by:
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Justin Swartz authored
Extract a magic number, from mt7621_spi_probe(), used to declare the number of chip select lines (which co-incides with the native chip select count of 2) to a macro. Use the newly defined MT7621_NATIVE_CS_COUNT macro to instead populate both the spi_controller's max_native_cs and num_chipselect members. Declare that the spi_controller should use_gpio_descriptors if present in the device properties (such as those declared in the cs-gpio property of a "ralink,mt7621-spi" compatible device-tree node) so that the SPI core will recalculcate num_chipselect to account for the GPIO descriptors that it should have populated in the cs_gpiod array member. Remove the assignment of mt7621_spi_transfer_one_message() to the spi_controller's transfer_one_message hook. Refactor the mt7621_spi_transfer_one_message() logic into mt7621_spi_prepare_message() and mt7621_spi_transfer_one() and assign both to the spi_controller's prepare_message and transfer_one hooks respectively. Migrate the call mt7621_spi_transfer_one_message() made to mt7621_spi_flush() just before chip select deactivation, to the end of mt7621_spi_write_half_duplex() to ensure that any pending data is shifted out of MOSI before the SPI core deactivates the chip select line. As chip select activation is now taken care of by the SPI core, due to the use of the transfer_one hook instead of transfer_one_message, the calls to mt7621_spi_set_cs() from mt7621_spi_transfer_one_message() have fallen away. And although the SPI core will handle activation for GPIO chip select lines behind the scenes, it requires a callback to allow the driver to perform controller-specific operations to control its native chip select lines. Rename mt7621_spi_set_cs() to mt7621_spi_set_native_cs() and make sure that it takes into account the activation polarity of the chip select line it's acting upon, as the passed enable parameter represents the desired line level and not the desired activation state, and then assign mt7621_set_cs() to the spi_controller's set_cs hook. Signed-off-by:
Justin Swartz <justin.swartz@risingedge.co.za> Link: https://msgid.link/r/20240316010302.20776-1-justin.swartz@risingedge.co.zaReviewed-by:
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Andy Shevchenko authored
There is nothing from pxa2xx_spi.h used by soc/pxa/ssp.c. Replace it with pxa2xx_ssp.h. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Link: https://msgid.link/r/20240307195056.4059864-4-andriy.shevchenko@linux.intel.comSigned-off-by:
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Andy Shevchenko authored
There is no use for whole 16-bit for the number of chip select pins. Drop it to 8 bits. Acked-by:
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Andy Shevchenko authored
There is the only one user of the pxa2xx_set_spi_info(). Unexport it and inline to the actual user. Signed-off-by:
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