1. 31 Oct, 2023 8 commits
    • Paolo Bonzini's avatar
      Merge tag 'kvm-x86-xen-6.7' of https://github.com/kvm-x86/linux into HEAD · e122d7a1
      Paolo Bonzini authored
      KVM x86 Xen changes for 6.7:
      
       - Omit "struct kvm_vcpu_xen" entirely when CONFIG_KVM_XEN=n.
      
       - Use the fast path directly from the timer callback when delivering Xen timer
         events.  Avoid the problematic races with using the fast path by ensuring
         the hrtimer isn't running when (re)starting the timer or saving the timer
         information (for userspace).
      
       - Follow the lead of upstream Xen and ignore the VCPU_SSHOTTMR_future flag.
      e122d7a1
    • Paolo Bonzini's avatar
      Merge tag 'kvm-x86-mmu-6.7' of https://github.com/kvm-x86/linux into HEAD · f0f59d06
      Paolo Bonzini authored
      KVM x86 MMU changes for 6.7:
      
       - Clean up code that deals with honoring guest MTRRs when the VM has
         non-coherent DMA and host MTRRs are ignored, i.e. EPT is enabled.
      
       - Zap EPT entries when non-coherent DMA assignment stops/start to prevent
         using stale entries with the wrong memtype.
      
       - Don't ignore guest PAT for CR0.CD=1 && KVM_X86_QUIRK_CD_NW_CLEARED=y, as
         there's zero reason to ignore guest PAT if the effective MTRR memtype is WB.
         This will also allow for future optimizations of handling guest MTRR updates
         for VMs with non-coherent DMA and the quirk enabled.
      
       - Harden the fast page fault path to guard against encountering an invalid
         root when walking SPTEs.
      f0f59d06
    • Paolo Bonzini's avatar
      Merge tag 'kvm-x86-misc-6.7' of https://github.com/kvm-x86/linux into HEAD · f292dc8a
      Paolo Bonzini authored
      KVM x86 misc changes for 6.7:
      
       - Add CONFIG_KVM_MAX_NR_VCPUS to allow supporting up to 4096 vCPUs without
         forcing more common use cases to eat the extra memory overhead.
      
       - Add IBPB and SBPB virtualization support.
      
       - Fix a bug where restoring a vCPU snapshot that was taken within 1 second of
         creating the original vCPU would cause KVM to try to synchronize the vCPU's
         TSC and thus clobber the correct TSC being set by userspace.
      
       - Compute guest wall clock using a single TSC read to avoid generating an
         inaccurate time, e.g. if the vCPU is preempted between multiple TSC reads.
      
       - "Virtualize" HWCR.TscFreqSel to make Linux guests happy, which complain
          about a "Firmware Bug" if the bit isn't set for select F/M/S combos.
      
       - Don't apply side effects to Hyper-V's synthetic timer on writes from
         userspace to fix an issue where the auto-enable behavior can trigger
         spurious interrupts, i.e. do auto-enabling only for guest writes.
      
       - Remove an unnecessary kick of all vCPUs when synchronizing the dirty log
         without PML enabled.
      
       - Advertise "support" for non-serializing FS/GS base MSR writes as appropriate.
      
       - Use octal notation for file permissions through KVM x86.
      
       - Fix a handful of typo fixes and warts.
      f292dc8a
    • Paolo Bonzini's avatar
      Merge tag 'kvm-x86-docs-6.7' of https://github.com/kvm-x86/linux into HEAD · fadaf574
      Paolo Bonzini authored
      KVM x86 Documentation updates for 6.7:
      
       - Fix various typos, notably a confusing reference to the non-existent
         "struct kvm_vcpu_event" (the actual structure is kvm_vcpu_events, plural).
      
       - Update x86's kvm_mmu_page documentation to bring it closer to the code
         (this raced with the removal of async zapping and so the documentation is
         already stale; my bad).
      
       - Document the behavior of x86 PMU filters on fixed counters.
      fadaf574
    • Paolo Bonzini's avatar
      Merge tag 'kvm-x86-apic-6.7' of https://github.com/kvm-x86/linux into HEAD · f2336467
      Paolo Bonzini authored
      KVM x86 APIC changes for 6.7:
      
       - Purge VMX's posted interrupt descriptor *before* loading APIC state when
         handling KVM_SET_LAPIC.  Purging the PID after loading APIC state results in
         lost APIC timer IRQs as the APIC timer can be armed as part of loading APIC
         state, i.e. can immediately pend an IRQ if the expiry is in the past.
      
       - Clear the ICR.BUSY bit when handling trap-like x2APIC writes.  This avoids a
         WARN, due to KVM expecting the BUSY bit to be cleared when sending IPIs.
      f2336467
    • Paolo Bonzini's avatar
      Merge tag 'kvm-s390-next-6.7-1' of... · 140139c5
      Paolo Bonzini authored
      Merge tag 'kvm-s390-next-6.7-1' of https://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEAD
      
      - nested page table management performance counters
      140139c5
    • Paolo Bonzini's avatar
      Merge tag 'kvm-riscv-6.7-1' of https://github.com/kvm-riscv/linux into HEAD · 957eedc7
      Paolo Bonzini authored
      KVM/riscv changes for 6.7
      
      - Smstateen and Zicond support for Guest/VM
      - Virtualized senvcfg CSR for Guest/VM
      - Added Smstateen registers to the get-reg-list selftests
      - Added Zicond to the get-reg-list selftests
      - Virtualized SBI debug console (DBCN) for Guest/VM
      - Added SBI debug console (DBCN) to the get-reg-list selftests
      957eedc7
    • Paolo Bonzini's avatar
      Merge tag 'loongarch-kvm-6.7' of... · ef12ea62
      Paolo Bonzini authored
      Merge tag 'loongarch-kvm-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson into HEAD
      
      LoongArch KVM changes for v6.7
      
      Add LoongArch's KVM support. Loongson 3A5000/3A6000 supports hardware
      assisted virtualization. With cpu virtualization, there are separate
      hw-supported user mode and kernel mode in guest mode. With memory
      virtualization, there are two-level hw mmu table for guest mode and host
      mode. Also there is separate hw cpu timer with consant frequency in
      guest mode, so that vm can migrate between hosts with different freq.
      Currently, we are able to boot LoongArch Linux Guests.
      
      Few key aspects of KVM LoongArch added by this series are:
      1. Enable kvm hardware function when kvm module is loaded.
      2. Implement VM and vcpu related ioctl interface such as vcpu create,
         vcpu run etc. GET_ONE_REG/SET_ONE_REG ioctl commands are use to
         get general registers one by one.
      3. Hardware access about MMU, timer and csr are emulated in kernel.
      4. Hardwares such as mmio and iocsr device are emulated in user space
         such as IPI, irqchips, pci devices etc.
      ef12ea62
  2. 30 Oct, 2023 1 commit
  3. 28 Oct, 2023 15 commits
  4. 27 Oct, 2023 15 commits
  5. 26 Oct, 2023 1 commit
    • Linus Torvalds's avatar
      Merge tag 'soc-fixes-6.7-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc · 3a568e3a
      Linus Torvalds authored
      Pull ARM SoC fixes from Arnd Bergmann:
       "A couple of platforms have some last-minute fixes, in particular:
      
         - riscv gets some fixes for noncoherent DMA on the renesas and thead
           platforms and dts fix for SPI on the visionfive 2 board
      
         - Qualcomm Snapdragon gets three dts fixes to address board specific
           regressions on the pmic and gpio nodes
      
         - Rockchip platforms get multiple dts fixes to address issues on the
           recent rk3399 platform as well as the older rk3128 platform that
           apparently regressed a while ago.
      
         - TI OMAP gets some trivial code and dts fixes and a regression fix
           for the omap1 ams-delta modem
      
         - NXP i.MX firmware has one fix for a use-after-free but in its error
           handling"
      
      * tag 'soc-fixes-6.7-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits)
        soc: renesas: ARCH_R9A07G043 depends on !RISCV_ISA_ZICBOM
        riscv: only select DMA_DIRECT_REMAP from RISCV_ISA_ZICBOM and ERRATA_THEAD_PBMT
        riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT
        riscv: dts: thead: set dma-noncoherent to soc bus
        arm64: dts: rockchip: Fix i2s0 pin conflict on ROCK Pi 4 boards
        arm64: dts: rockchip: Add i2s0-2ch-bus-bclk-off pins to RK3399
        clk: ti: Fix missing omap5 mcbsp functional clock and aliases
        clk: ti: Fix missing omap4 mcbsp functional clock and aliases
        ARM: OMAP1: ams-delta: Fix MODEM initialization failure
        soc: renesas: Make ARCH_R9A07G043 depend on required options
        riscv: dts: starfive: visionfive 2: correct spi's ss pin
        firmware/imx-dsp: Fix use_after_free in imx_dsp_setup_channels()
        ARM: OMAP: timer32K: fix all kernel-doc warnings
        ARM: omap2: fix a debug printk
        ARM: dts: rockchip: Fix timer clocks for RK3128
        ARM: dts: rockchip: Add missing quirk for RK3128's dma engine
        ARM: dts: rockchip: Add missing arm timer interrupt for RK3128
        ARM: dts: rockchip: Fix i2c0 register address for RK3128
        arm64: dts: rockchip: set codec system-clock-fixed on px30-ringneck-haikou
        arm64: dts: rockchip: use codec as clock master on px30-ringneck-haikou
        ...
      3a568e3a