- 18 Sep, 2019 1 commit
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Alex Deucher authored
We can remove this later as things get closer to launch. Reviewed-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 17 Sep, 2019 28 commits
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Tianci.Yin authored
Add Navi12 PCI id support. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
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Tianci.Yin authored
Add the navi14 PCI device id. Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Jay Cornwall authored
ttmp[4:5] hold information useful to the debugger. Use ttmp[14:15] instead, aligning implementation with gfx9 trap handler. Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Reviewed-by:
shaoyun liu <Shaoyun.liu@amd.com> Signed-off-by:
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Prike Liang authored
With the common interface print_clk_levels can get the following dpm clock: -pp_dpm_dcefclk -pp_dpm_fclk -pp_dpm_mclk -pp_dpm_sclk -pp_dpm_socclk Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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Kai-Heng Feng authored
Laptops with AMD APU doesn't restore display backlight brightness after system resume. This issue started when DC was introduced. Let's use BL_CORE_SUSPENDRESUME so the backlight core calls update_status callback after system resume to restore the backlight level. Tested on Dell Inspiron 3180 (Stoney Ridge) and Dell Latitude 5495 (Raven Ridge). Cc: <stable@vger.kernel.org> Signed-off-by:
Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by:
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Bhawanpreet Lakha authored
[Why] we only want the lowest voltage to be available for dali. [How] Use the get_highest_allowed_voltage_level function to return 0 for dali Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
Dali is a new asic revision based on raven2 Add the ID and ASICREV_IS_DALI define Signed-off-by:
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Felix Kuehling authored
Hawaii needs to flush caches explicitly, submitting an IB in a user VMID from kernel mode. There is no s_fence in this case. Fixes: eb3961a5 ("drm/amdgpu: remove fence context from the job") Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Prike Liang authored
The sdma_v4 should be ungated when the IP resume back, otherwise it will hang up and resume time out error. Signed-off-by:
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Trek authored
Do not try to allocate any amount of memory requested by the user. Instead limit it to 128 registers. Actually the longest series of consecutive allowed registers are 48, mmGB_TILE_MODE0-31 and mmGB_MACROTILE_MODE0-15 (0x2644-0x2673). Bug: https://bugs.freedesktop.org/show_bug.cgi?id=111273Signed-off-by:
Trek <trek00@inbox.ru> Signed-off-by:
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Hans de Goede authored
Bail from the pci_driver probe function instead of from the drm_driver load function. This avoid /dev/dri/card0 temporarily getting registered and then unregistered again, sending unwanted add / remove udev events to userspace. Specifically this avoids triggering the (userspace) bug fixed by this plymouth merge-request: https://gitlab.freedesktop.org/plymouth/plymouth/merge_requests/59 Note that despite that being an userspace bug, not sending unnecessary udev events is a good idea in general. BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1490490Reviewed-by:
Michel Dänzer <mdaenzer@redhat.com> Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
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Zhan Liu authored
[Why] When more than 2 displays are connected to the graphics card, only the minimum memory clock is needed. However, when more displays are connected, the minimum memory clock is not sufficient enough to support the overwhelming bandwidth. System will hang under this circumstance. Also, the old code didn't address HBM cards, which has 2 pseudo channels. We need to add the HBM part here. [How] When graphics card connects to 2 or more displays, switch to high memory clock. Also, choose memory multiplier based on whether its regular DRAM or HBM. Signed-off-by:
Zhan Liu <zhan.liu@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Charlene Liu authored
[Description] 1. OUTSTANDING_REQUEST_LIMIT update from 0xFF to 0x1F (HW doc update) 2. using memory type to convert UMC's MCLK to Yclk. Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Aaron Liu authored
These is no LBPW on Renoir. So removing program of lbpw for renoir. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
Restoring clock gating break SMU opeartion afterwards, avoid this until this further invistigated with SMU. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-and-tested-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Protect from concurrent SMU accesses. Signed-off-by:
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Aaron Liu authored
This patch updates MP1_BASE in renoir_ip_offset.h Signed-off-by:
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Aaron Liu authored
With stutter mode enabled, NMI prints frequently. Disable stutter for the moment because NMI warning storm, and will enable it back till the issue is addressed Signed-off-by:
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Roman Li authored
[Why] The earlier patch "Hook up calls to do stereo mux and dig programming..." doesn't include update for dcn21. [How] Align dcn21 gpio settings with updated stereo control interface. Signed-off-by:
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git://github.com/skeggsb/linuxDave Airlie authored
A couple of fixes from Thierry fixing issues as a result of the reservation object rework in this cycle, as well as a fix from Lyude to allow the driver to load on Thinkpad P71. Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Ben Skeggs <skeggsb@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CACAvsv5bLthhq7kh04A0JKxGnBdOTCxiu0hs7FZ1x3_9Rc9YoA@mail.gmail.com
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Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2019-09-11' of git://anongit.freedesktop.org/drm/drm-intel into drm-next Few fixes on GGTT and PPGTT around pin, locks, fence and vgpu. This also includes GVT fixes with two recent fixes: one for recent guest hang regression and another for guest reset fix. Signed-off-by:
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2019-09-06' of git://anongit.freedesktop.org/drm/drm-misc into drm-next - A significant number of panfrost fixes for runtime_pm, MMU and GEM support - A fix for DCS transfers on mcde Signed-off-by:
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https://gitlab.freedesktop.org/drm/msmDave Airlie authored
+ move msm8998 (snapdragon 835) display support + dpu fixes/cleanup + better async commit support for cursor updates (for dpu for now, I'll add mdp5 and possibly mdp4 once the movers deliver boxes full of my older hardware, so for v5.5) Signed-off-by:
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Thierry Reding authored
Writing the 0x1704 (BUS_BAR1_BLOCK) register causes the GPU to probe the memory region at the programmed address. The result is an address decode error in the external memory controller because address 0, which is what is written to the register, is not designated as accessible to devices. Avoid triggering DMA from the GPU by removing teardown of the BAR1. Signed-off-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Thierry Reding authored
When the last reference to a TTM BO is dropped, ttm_bo_release() will acquire the DMA reservation object's wound/wait mutex while trying to clean up (ttm_bo_cleanup_refs_or_queue() via ttm_bo_release()). It is therefore essential that drm_gem_object_release() be called after the TTM BO has been uninitialized, otherwise drm_gem_object_release() has already destroyed the wound/wait mutex (via dma_resv_fini()). Signed-off-by:
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Thierry Reding authored
Prior to commit 019cbd4a ("drm/nouveau: Initialize GEM object before TTM object"), the reservation object was locked across all of the buffer object creation. After splitting nouveau_bo_new() into separate nouveau_bo_alloc() and nouveau_bo_init() functions, the reservation object is passed to the latter, so the lock needs to be held across that function as well. Fixes: 019cbd4a ("drm/nouveau: Initialize GEM object before TTM object") Signed-off-by:
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Thierry Reding authored
Commit 019cbd4a ("drm/nouveau: Initialize GEM object before TTM object") introduced a subtle change in how the buffer allocation size is handled. Prior to that change, the size would get aligned to at least a page, whereas after that change a non-page-aligned size would get passed through unmodified. This ultimately causes a BUG_ON() to trigger in drm_gem_private_object_init() and crashes the system. Fix this by restoring the code that align the allocation size. Fixes: 019cbd4a ("drm/nouveau: Initialize GEM object before TTM object") Reported-by:
Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by:
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Lyude Paul authored
On the ThinkPad P71, we have one eDP connector exposed along with 5 DP connectors, resulting in a total of 11 TMDS encoders. Since the GPU on this system is also capable of MST, we create an additional 4 fake MST encoders for each DP port. Unfortunately, we also do this for the eDP port as well, resulting in: 1 eDP port: +1 TMDS encoder +4 DPMST encoders 5 DP ports: +2 TMDS encoders +4 DPMST encoders *5 ports == 35 encoders Which breaks things, since DRM has a hard coded limit of 32 encoders. So, fix this by not creating MSTMs for any eDP connectors. This brings us down to 31 encoders, although we can do better. This fixes driver probing for nouveau on the ThinkPad P71. Signed-off-by:Lyude Paul <lyude@redhat.com> Cc: stable@vger.kernel.org Signed-off-by:
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- 06 Sep, 2019 9 commits
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Chris Wilson authored
The intention is that we first try to pin the current vma into the mappable aperture only if it is already in use or it fits in the free space and will not cause contention. The first attempt was meant to be using PIN_NOEVICT to reuse the current vma if possible, following up with different eviction strategies. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111485 Fixes: 6846895f ("drm/i915: Replace PIN_NONFAULT with calls to PIN_NOEVICT") Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190826130750.17272-1-chris@chris-wilson.co.uk (cherry picked from commit ebfdf5cd) Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com>
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Xiaolin Zhang authored
vgpu ppgtt notification was split into 2 steps, the first step is to update PVINFO's pdp register and then write PVINFO's g2v_notify register with action code to tirgger ppgtt notification to GVT side. currently these steps were not atomic operations due to no any protection, so it is easy to enter race condition state during the MTBF, stress and IGT test to cause GPU hang. the solution is to add a lock to make vgpu ppgtt notication as atomic operation. Cc: stable@vger.kernel.org Signed-off-by:
Xiaolin Zhang <xiaolin.zhang@intel.com> Acked-by:
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Chris Wilson authored
Our fence management is lazy, very lazy. If the user marks an object as untiled, we do not immediately flush the fence but merely mark it as dirty. On the next use we have to remember to check and remove the fence, by which time we hope it is idle and we do not have to wait. v2: Throw away the old fence on the next ggtt_pin. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111468 Fixes: 1f7fd484 ("drm/i915: Replace i915_vma_put_fence()") Signed-off-by:
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Chris Wilson authored
Sadly lockdep records when the irqs are re-enabled and then marks up the fake lock as being irq-unsafe. Our hand is forced and so we must mark up the entire fake lock critical section as irq-off. Hopefully this is the last tweak required! v2: Not quite, we need to mark the timeline spinlock as irqsafe. That was a genuine bug being hidden by the earlier lockdep splat. Fixes: d6773926 ("drm/i915/gt: Mark up the nested engine-pm timeline lock as irqsafe") Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190823132700.25286-2-chris@chris-wilson.co.uk (cherry picked from commit 6dcb85a0) Signed-off-by:
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https://github.com/intel/gvt-linuxRodrigo Vivi authored
Merge tag 'gvt-next-fixes-2019-09-06' of https://github.com/intel/gvt-linux into drm-intel-next-fixes gvt-next-fixes-2019-09-06 - Fix guest context head pointer update for hang (Xiaolin) - Fix guest context ring state for reset (Weinan) Signed-off-by:
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https://git.pengutronix.de/git/lst/linuxDave Airlie authored
single etnaviv fix for an error path. Signed-off-by:
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
drm-next-5.4-2019-08-30: amdgpu: - Add DC support for Renoir - Add some GPUVM hw bug workarounds - add support for the smu11 i2c controller - GPU reset vram lost bug fixes - Navi1x powergating fixes - Navi12 power fixes - Renoir power fixes - Misc bug fixes and cleanups Signed-off-by:
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Weinan Li authored
The guest may use this register to identify the running state of one context. Emulate it as the value in context image as if the context runs on the GPU hardware. Signed-off-by:
Weinan Li <weinan.z.li@intel.com> Reviewed-by:
Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by:
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Xiaolin Zhang authored
when creating a vGPU workload, the guest context head pointer should be updated correctly by comparing with the exsiting workload in the guest worklod queue including the current running context. in some situation, there is a running context A and then received 2 new vGPU workload context B and A. in the new workload context A, it's head pointer should be updated with the running context A's tail. v2: walk through guest workload list in backward way. Cc: stable@vger.kernel.org Signed-off-by:
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- 04 Sep, 2019 2 commits
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Linus Walleij authored
There were bugs in the DSI transfer (read and write) function as it was only tested with displays ever needing a single byte to be written. Fixed it up and tested so we can now write messages of up to 16 bytes and read up to 4 bytes from the display. Tested with a Sony ACX424AKP display: this display now self- identifies and can control backlight in command mode. Reported-by:
kbuild test robot <lkp@intel.com> Fixes: 5fc537bf ("drm/mcde: Add new driver for ST-Ericsson MCDE") Reviewed-by:
Stephan Gerhold <stephan@gerhold.net> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190903170804.17053-1-linus.walleij@linaro.org
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Rob Clark authored
Looks like the dma_sync calls don't do what we want on armv7 either. Fixes: Unable to handle kernel paging request at virtual address 50001000 pgd = (ptrval) [50001000] *pgd=00000000 Internal error: Oops: 805 [#1] SMP ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.3.0-rc6-00271-g9f159ae0 #4 Hardware name: Freescale i.MX53 (Device Tree Support) PC is at v7_dma_clean_range+0x20/0x38 LR is at __dma_page_cpu_to_dev+0x28/0x90 pc : [<c011c76c>] lr : [<c01181c4>] psr: 20000013 sp : d80b5a88 ip : de96c000 fp : d840ce6c r10: 00000000 r9 : 00000001 r8 : d843e010 r7 : 00000000 r6 : 00008000 r5 : ddb6c000 r4 : 00000000 r3 : 0000003f r2 : 00000040 r1 : 50008000 r0 : 50001000 Flags: nzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none Control: 10c5387d Table: 70004019 DAC: 00000051 Process swapper/0 (pid: 1, stack limit = 0x(ptrval)) Signed-off-by:
Rob Clark <robdclark@chromium.org> Fixes: 3de433c5 ("drm/msm: Use the correct dma_sync calls in msm_gem") Tested-by:
Fabio Estevam <festevam@gmail.com>
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