- 08 Jun, 2021 37 commits
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Sergey Ryazanov authored
It is quite common for a userpace program to fetch the buffered amount of data in the rx queue to avoid the read block. Implement the TIOCINQ ioctl to make the migration to the WWAN port usage smooth. Despite the fact that the read call will return no more data than the size of a first skb in the queue, TIOCINQ returns the entire amount of buffered data (sum of all queued skbs). This is done to prevent the breaking of programs that optimize reading, avoiding it if the buffered amount of data is too small. Signed-off-by:
Sergey Ryazanov <ryazanov.s.a@gmail.com> Reviewed-by:
Loic Poulain <loic.poulain@linaro.org> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Sergey Ryazanov authored
Currently, we limit the total ports number to 256. It is quite common for PBX or SMS gateway to be equipped with a lot of modems. In now days, a modem could have 2-4 control ports or even more, what only accelerates the ports exhausing rate. To avoid facing the port number limitation issue reports, increase the limit up the maximum number of minors (i.e. up to 1 << MINORBITS). Signed-off-by:
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Sergey Ryazanov authored
At the moment, the port name is allocated based on the parent device name, port id and the port type. Where the port id specifies nothing but the ports registration order and is only used to make the port name unique. Most likely, to configure a WWAN device, the user will look for a port of a specific type (e.g. AT port or MBIM port, etc.). The current naming scheme can make it difficult to find a port of a specific type. Consider a WWAN device that has 3 ports: AT port, MBIM port, and another one AT port. With the global port index, the port names will be: * wwan0p1at * wwan0p2mbim * wwan0p3at To find the MBIM port, user should know in advance the device ports composition (i.e. the user should know that the MBIM port is the 2nd one) or carefully examine the whole ports list. It is not unusual for USB modems to have a different composition, even if they are build on a same chipset. Moreover, some modems able to change the ports composition based on the user's configuration. All this makes port names fully unpredictable. To make naming more user-friendly, remove the global port id and enumerate ports by its type. E.g.: * wwan0p1at -> wwan0at0 * wwan0p2mbim -> wwan0mbim0 * wwan0p3at -> wwan0at1 With this naming scheme, the first AT port name will always be wwanXat0, the first MBIM port name will always be wwanXmbim0, etc. Signed-off-by:
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Sergey Ryazanov authored
Usually a device name is spelled in lowercase, let us follow this practice in the WWAN subsystem as well. The bottom line is that such name is easier to type. To keep the device type attribute contents more natural (i.e., spell abbreviations in uppercase), while making the device name lowercase, turn the port type strings array to an array of structure that contains both the port type name and the device name suffix. Signed-off-by:
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Sergey Ryazanov authored
This array is indexed by port type. Make it self-descriptive by using the port type enum values as indices in the array initializer. Signed-off-by:
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Sergey Ryazanov authored
It is quite unusual when some value can not be equal to a defined range max value. Also most subsystems defines FOO_TYPE_MAX as a maximum valid value. So turn the WAN_PORT_MAX meaning from the number of supported port types to the maximum valid port type. Signed-off-by:
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Sergey Ryazanov authored
wwan_hwsim creates and removes simulated control ports on module loading and unloading. It would be helpful to be able to create/remove devices and ports at run-time to trigger wwan port (un-)register actions without module reloading. Some simulator objects (e.g. ports) do not have the underling device and it is not possible to fully manage the simulator via sysfs. wwan_hsim intend for developers, so implement it as a self-contained debugfs based management interface. Signed-off-by:
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Sergey Ryazanov authored
This driver simulates a set of WWAN device with a set of AT control ports. It can be used to test WWAN kernel framework as well as user space tools. Signed-off-by:
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David S. Miller authored
Michael Sit Wei Hong says: ==================== Enable 2.5Gbps speed for stmmac Intel mGbE supports 2.5Gbps link speed by overclocking the clock rate by 2.5 times to support 2.5Gbps link speed. In this mode, the serdes/PHY operates at a serial baud rate of 3.125 Gbps and the PCS data path and GMII interface of the MAC operate at 312.5 MHz instead of 125 MHz. This is configured in the BIOS during boot up. The kernel driver is not able access to modify the clock rate for 1Gbps/2.5G mode on the fly. The way to determine the current 1G/2.5G mode is by reading a dedicated adhoc register through mdio bus. Changes: v5 -> v6 patch 1/3 - Check if mdio_bus_data is populated to prevent NULL pointer dereferencing when accesing mdio_bus_data member v4 -> v5 patch 1/3 - Rebase to latest code changes after Vladimir's code is merged and fix build warnings v3 -> v4 patch 1/3 - Rebase to latest code and Initialize 'found' to 0 to avoid build warning patch 2/3 - Fix indentation issue from v3 v2 -> v3 patch 1/3 -New patch added to restructure the code. enabling reading the dedicated adhoc register to determine link speed mode. patch 2/3 -Restructure for 2.5G speed to use 2500BaseX configuration as the PHY interface. patch 3/3 -Restructure to read serdes registers to set max_speed and configure to use 2500BaseX in 2.5G speeds. v1 -> v2 patch 1/2 -Remove MAC supported link speed masking patch 2/2 -Add supported link speed masking in the PCS iperf3 and ping for 2.5Gbps and regression test on 10M/100M/1000Mbps is done to prevent regresson issues. ==================== Signed-off-by: -
Voon Weifeng authored
The Intel mGbE supports 2.5Gbps link speed by increasing the clock rate by 2.5 times of the original rate. In this mode, the serdes/PHY operates at a serial baud rate of 3.125 Gbps and the PCS data path and GMII interface of the MAC operate at 312.5 MHz instead of 125 MHz. For Intel mGbE, the overclocking of 2.5 times clock rate to support 2.5G is only able to be configured in the BIOS during boot time. Kernel driver has no access to modify the clock rate for 1Gbps/2.5G mode. The way to determined the current 1G/2.5G mode is by reading a dedicated adhoc register through mdio bus. In short, after the system boot up, it is either in 1G mode or 2.5G mode which not able to be changed on the fly. Compared to 1G mode, the 2.5G mode selects the 2500BASEX as PHY interface and disables the xpcs_an_inband. This is to cater for some PHYs that only supports 2500BASEX PHY interface with no autonegotiation. v2: remove MAC supported link speed masking v3: Restructure to introduce intel_speed_mode_2500() to read serdes registers for max speed supported and select the appropritate configuration. Use max_speed to determine the supported link speed mask. Signed-off-by:Voon Weifeng <weifeng.voon@intel.com> Signed-off-by:
Michael Sit Wei Hong <michael.wei.hong.sit@intel.com> Reviewed-by:
Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by:
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Voon Weifeng authored
XPCS IP supports 2500BASEX as PHY interface. It is configured as autonegotiation disable to cater for PHYs that does not supports 2500BASEX autonegotiation. v2: Add supported link speed masking. v3: Restructure to introduce xpcs_config_2500basex() used to configure the xpcs for 2.5G speeds. Added 2500BASEX specific information for configuration. v4: Fix indentation error Signed-off-by: -
Voon Weifeng authored
This patch is a preparation patch for the enabling of Intel mGbE 2.5Gbps link speed. The Intel mGbR link speed configuration (1G/2.5G) is depends on a mdio ADHOC register which can be configured in the bios menu. As PHY interface might be different for 1G and 2.5G, the mdio bus need be ready to check the link speed and select the PHY interface before probing the xPCS. Signed-off-by:
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git://git.open-mesh.org/linux-mergeDavid S. Miller authored
Simon Wunderlich says: ==================== pull request for net-next: batman-adv 2021-06-08 here is a feature/cleanup pull request of batman-adv to go into net-next. Please pull or let me know of any problem! This feature/cleanup patchset includes the following patches: - bump version strings, by Simon Wunderlich - consistently send iface index/name in genlmsg, by Sven Eckelmann - improve broadcast queueing, by Linus Lüssing (2 patches) - add support for routable IPv4 multicast with bridged setups, by Linus Lüssing - remove repeated declarations, by Shaokun Zhang - fix spelling mistakes, by Zheng Yongjun - clean up hard interface handling after dropping sysfs support, by Sven Eckelmann (4 patches) ==================== Signed-off-by: -
Geert Uytterhoeven authored
The help text for the symbol controlling support for the NVM Express over Fabrics TCP offload common layer suggests to not enable this support when unsure. Hence drop the "default m", which actually means "default y" if CONFIG_MODULES is not enabled. Fixes: f0e8cb61 ("nvme-tcp-offload: Add nvme-tcp-offload - NVMeTCP HW offload ULP") Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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David S. Miller authored
Peng Li says: ==================== net: farsync: clean up some code style issues This patchset clean up some code style issues. ==================== Signed-off-by: -
Peng Li authored
According to the chackpatch.pl, comparison to NULL could be written "fst_card_array[i]". Signed-off-by:
Peng Li <lipeng321@huawei.com> Signed-off-by:
Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by:
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Peng Li authored
Void function return statements are not generally useful. Signed-off-by:
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Peng Li authored
Alignment should match open parenthesis. Signed-off-by:
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Peng Li authored
Unnecessary parentheses around 'port->hwif == X21'. Signed-off-by:
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Peng Li authored
According to the chackpatch.pl, space prohibited between function name and open parenthesis '(', no space is necessary after a cast. Signed-off-by: -
Peng Li authored
This patch removes redundant braces {}, to fix the checkpatch.pl warning: "braces {} are not necessary for single statement blocks". Signed-off-by: -
Peng Li authored
Add spaces required around that '=' and '*'. Signed-off-by:
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Peng Li authored
Macros with complex values should be enclosed in parentheses. space required after that ',' . Signed-off-by:
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Peng Li authored
Code indent should use tabs where possible. Signed-off-by:
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Peng Li authored
This patch removes trailing whitespaces. Signed-off-by:
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Peng Li authored
Networking block comments don't use an empty /* line, use /* Comment... Block comments use * on subsequent lines. Block comments use a trailing */ on a separate line. This patch fixes the comments style issues. Signed-off-by:
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Peng Li authored
Should not initialise statics to 0. Signed-off-by:
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Peng Li authored
Should not use assignment in if condition. Signed-off-by:
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Peng Li authored
Fix the checkpatch error as "foo * bar" should be "foo *bar". Signed-off-by:
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Peng Li authored
This patch fixes the checkpatch error about missing a blank line after declarations. Signed-off-by:
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Peng Li authored
This patch removes some redundant blank lines. Signed-off-by:
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David S. Miller authored
Joakim Zhang says: ==================== net: phy: add dt property for realtek phy Add dt property for realtek phy. --- ChangeLogs: V1->V2: * store the desired PHYCR1/2 register value in "priv" rather than using "quirks", per Russell King suggestion, as well as can cover the bootloader setting. * change the behavior of ALDPS mode, default is disabled, add dt property for users to enable it. * fix dt binding yaml build issues. ==================== Signed-off-by: -
Joakim Zhang authored
PHY will delay about 11.5ms to generate RXC clock when switching from power down to normal operation. Read/write registers would also cause RXC become unstable and stop for a while during this process. Realtek engineer suggests 15ms or more delay can workaround this issue. Signed-off-by:
Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by:
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Joakim Zhang authored
If enable Advance Link Down Power Saving (ALDPS) mode, it will change crystal/clock behavior, which cause RXC clock stop for dozens to hundreds of miliseconds. This is comfirmed by Realtek engineer. For some MACs, it needs RXC clock to support RX logic, after this patch, PHY can generate continuous RXC clock during auto-negotiation. ALDPS default is disabled after hardware reset, it's more reasonable to add a property to enable this feature, since ALDPS would introduce side effect. This patch adds dt property "realtek,aldps-enable" to enable ALDPS mode per users' requirement. Jisheng Zhang enables this feature, changes the default behavior. Since mine patch breaks the rule that new implementation should not break existing design, so Cc'ed let him know to see if it can be accepted. Cc: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by:
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Joakim Zhang authored
CLKOUT is enabled by default after PHY hardware reset, this patch adds "realtek,clkout-disable" property for user to disable CLKOUT clock to save PHY power. Per RTL8211F guide, a PHY reset should be issued after setting these bits in PHYCR2 register. After this patch, CLKOUT clock output to be disabled. Signed-off-by:
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Joakim Zhang authored
Add binding for realtek rtl82xx phy. Signed-off-by:
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Marek Behún authored
The BAREUDP config option uses spaces instead of tabs for indentation. The rest of this file uses tabs. Fix this. Signed-off-by:
Marek Behún <kabel@kernel.org> Signed-off-by:
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- 07 Jun, 2021 3 commits
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David S. Miller authored
Matteo Croce says: ==================== page_pool: recycle buffers This is a respin of [1] This patchset shows the plans for allowing page_pool to handle and maintain DMA map/unmap of the pages it serves to the driver. For this to work a return hook in the network core is introduced. The overall purpose is to simplify drivers, by providing a page allocation API that does recycling, such that each driver doesn't have to reinvent its own recycling scheme. Using page_pool in a driver does not require implementing XDP support, but it makes it trivially easy to do so. Instead of allocating buffers specifically for SKBs we now allocate a generic buffer and either wrap it on an SKB (via build_skb) or create an XDP frame. The recycling code leverages the XDP recycle APIs. The Marvell mvpp2 and mvneta drivers are used in this patchset to demonstrate how to use the API, and tested on a MacchiatoBIN and EspressoBIN boards respectively. Please let this going in on a future -rc1 so to allow enough time to have wider tests. v7 -> v8: - use page->lru.next instead of page->index for pfmemalloc - remove conditional include - rework page_pool_return_skb_page() so to have less conversions between page and addresses, and call compound_head() only once - move some code from skb_free_head() to a new helper skb_pp_recycle() - misc fixes v6 -> v7: - refresh patches against net-next - remove a redundant call to virt_to_head_page() - update mvneta benchmarks v5 -> v6: - preserve pfmemalloc bit when setting signature - fix typo in mvneta - rebase on next-next with the new cache - don't clear the skb->pp_recycle in pskb_expand_head() v4 -> v5: - move the signature so it doesn't alias with page->mapping - use an invalid pointer as magic - incorporate Matthew Wilcox's changes for pfmemalloc pages - move the __skb_frag_unref() changes to a preliminary patch - refactor some cpp directives - only attempt recycling if skb->head_frag - clear skb->pp_recycle in pskb_expand_head() v3 -> v4: - store a pointer to page_pool instead of xdp_mem_info - drop a patch which reduces xdp_mem_info size - do the recycling in the page_pool code instead of xdp_return - remove some unused headers include - remove some useless forward declaration v2 -> v3: - added missing SOBs - CCed the MM people v1 -> v2: - fix a commit message - avoid setting pp_recycle multiple times on mvneta - squash two patches to avoid breaking bisect ==================== Signed-off-by: -
Matteo Croce authored
Use the new recycling API for page_pool. In a drop rate test, the packet rate increased by 10%, from 296 Kpps to 326 Kpps. perf top on a stock system shows: Overhead Shared Object Symbol 23.66% [kernel] [k] __pi___inval_dcache_area 22.85% [mvneta] [k] mvneta_rx_swbm 7.54% [kernel] [k] kmem_cache_alloc 6.49% [kernel] [k] eth_type_trans 3.94% [kernel] [k] dev_gro_receive 3.91% [kernel] [k] __netif_receive_skb_core 3.91% [kernel] [k] kmem_cache_free 3.76% [kernel] [k] page_pool_release_page 3.56% [kernel] [k] free_unref_page 2.40% [kernel] [k] build_skb 1.49% [kernel] [k] skb_release_data 1.45% [kernel] [k] __alloc_pages_bulk 1.30% [kernel] [k] page_frag_free And this is the same output with recycling enabled: Overhead Shared Object Symbol 26.41% [kernel] [k] __pi___inval_dcache_area 25.00% [mvneta] [k] mvneta_rx_swbm 8.14% [kernel] [k] kmem_cache_alloc 6.84% [kernel] [k] eth_type_trans 4.44% [kernel] [k] __netif_receive_skb_core 4.38% [kernel] [k] kmem_cache_free 4.16% [kernel] [k] dev_gro_receive 3.21% [kernel] [k] page_pool_put_page 2.41% [kernel] [k] build_skb 1.82% [kernel] [k] skb_release_data 1.61% [kernel] [k] napi_gro_receive 1.25% [kernel] [k] page_pool_refill_alloc_cache 1.16% [kernel] [k] __netif_receive_skb_list_core We can see that page_pool_release_page(), free_unref_page() and __alloc_pages_bulk() are no longer on top of the list when receiving traffic. The test was done with mausezahn on the TX side with 64 byte raw ethernet frames. Signed-off-by:
Matteo Croce <mcroce@microsoft.com> Signed-off-by:
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Matteo Croce authored
Use the new recycling API for page_pool. In a drop rate test, the packet rate is almost doubled, from 1110 Kpps to 2128 Kpps. perf top on a stock system shows: Overhead Shared Object Symbol 34.88% [kernel] [k] page_pool_release_page 8.06% [kernel] [k] free_unref_page 6.42% [mvpp2] [k] mvpp2_rx 6.07% [kernel] [k] eth_type_trans 5.18% [kernel] [k] __netif_receive_skb_core 4.95% [kernel] [k] build_skb 4.88% [kernel] [k] kmem_cache_free 3.97% [kernel] [k] kmem_cache_alloc 3.45% [kernel] [k] dev_gro_receive 2.73% [kernel] [k] page_frag_free 2.07% [kernel] [k] __alloc_pages_bulk 1.99% [kernel] [k] arch_local_irq_save 1.84% [kernel] [k] skb_release_data 1.20% [kernel] [k] netif_receive_skb_list_internal With packet rate stable at 1100 Kpps: tx: 0 bps 0 pps rx: 532.7 Mbps 1110 Kpps tx: 0 bps 0 pps rx: 532.6 Mbps 1110 Kpps tx: 0 bps 0 pps rx: 532.4 Mbps 1109 Kpps tx: 0 bps 0 pps rx: 532.1 Mbps 1109 Kpps tx: 0 bps 0 pps rx: 531.9 Mbps 1108 Kpps tx: 0 bps 0 pps rx: 531.9 Mbps 1108 Kpps And this is the same output with recycling enabled: Overhead Shared Object Symbol 12.91% [kernel] [k] eth_type_trans 12.54% [mvpp2] [k] mvpp2_rx 9.67% [kernel] [k] build_skb 9.63% [kernel] [k] __netif_receive_skb_core 8.44% [kernel] [k] page_pool_put_page 8.07% [kernel] [k] kmem_cache_free 7.79% [kernel] [k] kmem_cache_alloc 6.86% [kernel] [k] dev_gro_receive 3.19% [kernel] [k] skb_release_data 2.41% [kernel] [k] netif_receive_skb_list_internal 2.18% [kernel] [k] page_pool_refill_alloc_cache 1.76% [kernel] [k] napi_gro_receive 1.61% [kernel] [k] kfree_skb 1.20% [kernel] [k] dma_sync_single_for_device 1.16% [mvpp2] [k] mvpp2_poll 1.12% [mvpp2] [k] mvpp2_read With packet rate above 2100 Kpps: tx: 0 bps 0 pps rx: 1021 Mbps 2128 Kpps tx: 0 bps 0 pps rx: 1021 Mbps 2127 Kpps tx: 0 bps 0 pps rx: 1021 Mbps 2128 Kpps tx: 0 bps 0 pps rx: 1021 Mbps 2128 Kpps tx: 0 bps 0 pps rx: 1022 Mbps 2128 Kpps tx: 0 bps 0 pps rx: 1022 Mbps 2129 Kpps The major performance increase is explained by the fact that the most CPU consuming functions (page_pool_release_page, page_frag_free and free_unref_page) are no longer called on a per packet basis. The test was done by sending to the macchiatobin 64 byte ethernet frames with an invalid ethertype, so the packets are dropped early in the RX path. Signed-off-by:
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