- 09 Apr, 2015 1 commit
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Julia Lawall authored
Put NULL test on the result of the previous call instead on one of its arguments. A simplified version of the semantic match that finds this problem is as follows (http://coccinelle.lip6.fr/): // <smpl> r@ expression *e1; expression *e2; identifier f; statement S1,S2; @@ e1 = f(...,e2,...); ( if (e1 == NULL || ...) S1 else S2 | *if (e2 == NULL || ...) S1 else S2 ) // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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- 08 Apr, 2015 1 commit
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Georgi Djakov authored
When we introduced the parent_map tables, we missed to update some of the functions where mapping is translated. Fix this. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Tested-by: Nicolas Dechesne <nicolas.dechesne@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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- 07 Apr, 2015 1 commit
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Bartlomiej Zolnierkiewicz authored
Support for Qualcomm's clock controllers should be available only on Qualcomm platforms. Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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- 06 Apr, 2015 1 commit
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Archit Taneja authored
The NAND controller within EBI2 requires EBI2_CLK and EBI2_ALWAYS_ON_CLK clocks. Create structs for these clocks so that they can be used by the NAND controller driver. Add an entry for EBI2_AON_CLK in the gcc-ipq806x DT binding document. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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- 01 Apr, 2015 2 commits
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Fabian Frederick authored
of_device_id is always used as const. (See driver.of_match_table and open firmware functions) __initdata updated to __initconst for static const struct of_device_id ti_clkdm_match_table[] Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Paul Walmsley authored
Most Linux clock framework discussions take place on the linux-kernel@vger.kernel.org or linux-arm-kernel@lists.infradead.org mailing lists. The volume of unrelated messages on these lists makes it difficult for non-maintainers to follow along with discussions. Switch the discussion list for clock framework discussions to linux-clk@vger.kernel.org. Also, add linux-clk@vger.kernel.org as a mailing list for clock API discussions. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Russell King <linux@arm.linux.org.uk> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
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- 30 Mar, 2015 2 commits
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Tomasz Figa authored
Add clock controller for CMU ISP clock domain on Exynos3250, providing clocks for FIMC-IS subsystem. [b.michalska: use samsung_cmu_register_one to register the provider; updated DT binding documentation] Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Beata Michalska <b.michalska@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> [s.nawrocki: added __init attribute which was missing in function exynos3250_cmu_platform_init() in function, which has been] Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
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Inha Song authored
This patch add CLKOUT driver support for Exynos3250 SoC. Exynos3250 SoC PMU_DEBUG is the same with Exynos4's PMU_DEBUG including CLKOUT mux. So we can use the exynos4's clkout init function for Exynos3250 without the need to add new function. Signed-off-by: Inha Song <ideal.song@samsung.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
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- 27 Mar, 2015 5 commits
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Krzysztof Kozlowski authored
The regmap_config struct may be const because it is not modified by the driver and regmap_init() accepts pointer to const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Krzysztof Kozlowski authored
The regmap_config struct may be const because it is not modified by the driver and regmap_init() accepts pointer to const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Krzysztof Kozlowski authored
The regmap_config struct may be const because it is not modified by the driver and regmap_init() accepts pointer to const. Replace doubled const in the arrays of clock names with proper const pointer to const data. This fixes the warnings: drivers/clk/clk-si5351.c:71:25: warning: duplicate const drivers/clk/clk-si5351.c:74:25: warning: duplicate const drivers/clk/clk-si5351.c:77:25: warning: duplicate const drivers/clk/clk-si5351.c:80:25: warning: duplicate const Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Fengguang Wu authored
drivers/clk/qcom/clk-pll.c:74:1-4: WARNING: end returns can be simpified Simplify a trivial if-return sequence. Possibly combine with a preceding function call. Generated by: scripts/coccinelle/misc/simple_return.cocci Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
These frequency tables list the wrong rates. Either they don't have the correct frequency at all, or they're specified in kHz instead of Hz. Fix it. Fixes: c99e515a "clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver" Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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- 25 Mar, 2015 3 commits
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Michael Turquette authored
Merge tag 'sunxi-clocks-for-4.1' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Allwinner clocks changes for 4.1 The usual round of clock changes for the Allwinner SoCs. There is nothing really standing out here, but a few changes and fixes, most notably to allow the AHB clock to be parented to a PLL, instead of the CPU clock to avoid any AHB rate change due to cpufreq.
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Chen-Yu Tsai authored
The pll6 has a /4 output that is used as an input to the ahb mux clock. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
The current sunxi clock driver has the base factor clock of divs clocks as the last clock output of the clock node. This makes it rather difficult to add new outputs, such as fixed dividers, which were previously unknown. This patch makes the divs clocks data structure specify which output is the factor clock, and updates all current divs clocks accordingly. We can then add new outputs after the factor clocks, at least not breaking backward compatibility with regards to the devicetree bindings. Also replace kzalloc with kcalloc in sunxi_divs_clk_setup(). Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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- 24 Mar, 2015 11 commits
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Michael Turquette authored
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Tony Lindgren authored
Since we have a fractional divider for the synthesizer, just implement a simple multiply logic for the PLL. It seems the PLL divider needs to have also the multiplier set for the PLL to lock. At least I have not yet figured out if divided rates are doable. So let's just ignore the PLL divider for now as the synthesizer has both integer and fractional dividers so we don't even need to use the PLL divider for the rates we know work with PLL locking. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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Tony Lindgren authored
We can pretty much get any rate out of the FAPLL because of the fractional divider. Let's first try just adjusting the post divider, and if that is not enough, then reprogram both the fractional divider and the post divider. Let's also add a define for the fixed SYNTH_PHASE_K instead of using 8. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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Tony Lindgren authored
We need to round the calculated value to have it match the requested rate. While at it, let's fix a typo and use a define for SYNTH_MAX_DIV_M as we will need it in later patches for set_rate. And let's remove two unused includes. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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Suman Anna authored
The OMAP DMTimer API, omap_dm_timer_set_source(), uses the clock name timer_sys_ck for setting a timer's clock source for the source index OMAP_TIMER_SRC_SYS_CLK. There is currently no clock alias data for the Timers 13 through 16 for this clock name, so add the same. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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Suman Anna authored
The OMAP DMTimer API, omap_dm_timer_set_source(), can set the parent of a timer node using 3 different values that use fixed parent names for the clocks. The parent name, timer_sys_ck, is used for setting the parent when used with the source index OMAP_TIMER_SRC_SYS_CLK. This should point to the TIMER_SYS_CLK and not the SYSCLKIN2, so correct the clock aliases appropriately. SYSCLKIN2 is not a mandatory clock input. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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Suman Anna authored
The DT clock aliases for Timers use the legacy (non-DT) device names and a source clock named sys_ck. OMAP5 is DT-boot only, so correct the DT clock aliases to use the DT device names instead. Also, the source clock name is corrected from 'sys_ck' to 'timer_sys_ck', the name used by the OMAP dmtimer driver. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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Suman Anna authored
The DT clock aliases for timers using the legacy OMAP timer device names have been cleaned up. These device names reflect the names used in legacy boot, and are no longer applicable as OMAP4 is DT boot only now. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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Peter Ujfalusi authored
Correct the McBSP2/4 ick mapping (they were 2->4 and 4->2). Add missing mcbsp clock aliases. Collect the McBSP clock definition in one location at the same time. Fixes the following warning on boot: [ 0.307739] omap_hwmod: mcbsp2: _wait_target_ready failed: -16 [ 0.307769] omap_hwmod: mcbsp2: cannot be enabled for reset (3) Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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Peter Ujfalusi authored
In DT boot we do not have devices named as omap-mcbsp.X. Correct the McBSP2/4 ick mapping (they were 2->4 and 4->2). Collect the McBSP clock definition in one location at the same time. Fixes the following warning on boot: [ 0.307739] omap_hwmod: mcbsp2: _wait_target_ready failed: -16 [ 0.307769] omap_hwmod: mcbsp2: cannot be enabled for reset (3) Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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Tero Kristo authored
There is a case where NULL can be a valid return value for ti_clk_get_reg_addr, specifically the case where both the provider index and register offsets are zero. In this case, the current error checking against a NULL pointer will fail. Thus, change the API to return a ERR_PTR value in an error case, and change all the users of this API to check against IS_ERR instead. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Michael Turquette <mturquette@linaro.org>
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- 23 Mar, 2015 7 commits
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Georgi Djakov authored
This patch adds support for the global clock controller found on the MSM8916 based devices. It allows the various device drivers to probe and control their clocks and resets. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> [sboyd@codeaurora.org: Removed NULL entry from parent_maps] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Georgi Djakov authored
Add clocks/resets defines for the global clock controller found on Qualcomm MSM8916 SoCs. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Georgi Djakov authored
In the current parent mapping code, we can get duplicate or inconsistent indexes, which leads to discrepancy between the number of elements in the array and the number of parents. Until now, this was solved with some reordering but this is not always possible. This patch introduces index tables that are used to define the relations between the PLL source and the hardware mux configuration value. To accomplish this, here we do the following: - Define a parent_map struct to map the relations between PLL source index and register configuration value. - Add a qcom_find_src_index() function for finding the index of a clock matching the specific PLL configuration. - Update the {set,get}_parent RCG functions use the newly introduced parent_map struct. - Convert all existing drivers to the new parent_map tables. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Georgi Djakov authored
Currently configure_bank() returns void. Add some error checking on the regmap calls and propagate if there is any error. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Georgi Djakov authored
According to the common clock framework API, the clk_get_parent() function should return u8. Currently we are returning negative values on error. Fix this and use the default parent in case of an error. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Archit Taneja authored
Currently, a RCG's M/N counter (used for fraction division) is set to either 'bypass' (counter disabled) or 'dual edge' (counter enabled) based on whether the corresponding rcg struct has a mnd field specified and a non-zero N. In the case where M and N are the same value, the M/N counter is still enabled by code even though no division takes place. Leaving the RCG in such a state can result in improper behavior. This was observed with the DSI pixel clock RCG when M and N were both set to 1. Add an additional check (M != N) to enable the M/N counter only when it's needed for fraction division. Signed-off-by: Archit Taneja <architt@codeaurora.org> Fixes: bcd61c0f (clk: qcom: Add support for root clock generators (RCGs)) Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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git://git.infradead.org/linux-mvebuMichael Turquette authored
clock changes for mvebu for v4.1 - Add clock support for Armada 39x
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- 21 Mar, 2015 3 commits
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Chen-Yu Tsai authored
We want to reparent AHB clock to PLL6 on sun5i/sun7i using the assigned clocks properties. AHB is a factor clock, while PLL6 is a divs clock. Register divs clocks before factor clocks so reparenting works. This is only needed because we do the reparenting on the clock provider. The proper way to fix this is to split out all the old sunxi clocks into separate CLK_OF_DECLARE statements, like we are doing for sun9i. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
Now that the ahb clock on sun5i/sun7i is muxable, ahb is no longer guaranteed to be a child of the cpu clock. Add the cpu clock to the list of protected clocks so it doesn't get disabled. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
The AHB clock on sun5i and sun7i are muxable divider clocks. Use a factors clock to support them. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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- 12 Mar, 2015 3 commits
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Stephen Boyd authored
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Stephen Boyd authored
of_clk_get_by_clkspec() has the same function signature as of_clk_get_from_provider() struct clk *of_clk_get_by_clkspec(struct of_phandle_args *clkspec) struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec) except of_clk_get_by_clkspec() checks to make sure clkspec is not NULL. Let's remove of_clk_get_by_clkspec() and replace the callers of it (clkconf.c) with of_clk_get_from_provider(). Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
The child_node member of struct clk is named the same as the child_node member of struct clk_core. Let's rename the struct clk's member to clks_node to avoid getting confused with the child_node member of struct clk_core and to match the name of the list head, clks. Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Cc: Alban Browaeys <alban.browaeys@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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