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- 11 Feb, 2007 2 commits
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Rafa Bilski authored
Borowed from VIA driver. Signed-off-by: Rafal Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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Rafa Bilski authored
Simple cleanup in code which is setting minmult. Signed-off-by: Rafal Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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- 04 Feb, 2007 2 commits
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Rafa Bilski authored
I don't know why it is working and how, but it is working. On my Epia transition time is by default set to 100us. I'm changing it to 200us. After that I can change frequency from min (x4.0) to max (x7.5) without lockup. Many times. There is a paranoid check at a beginning of a patch. Probably dead code, but I don't have better ideas for CL10000 case at the moment. Only way to to detect broken chip seems to be looking in log for spurious interrupts. Signed-off-by: Rafal Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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Rafa Bilski authored
This is bug reported by John-Marc Chandonia: > Detected 1002.292 MHz processor. > longhaul: VIA C3 'Nehemiah B' [C5N] CPU detected. Powersaver supported. > longhaul: Using throttling support. > longhaul: Invalid (reserved) FSB! FSB is correcly guessed for 999.554 MHz CPU. To fix this error: - ROUNDING should be range, not mask - at it's current value it is +7 -8, - more precise calculations inside guess_fsb - 7.5x133MHz is 1000MHz now. Signed-off-by: Rafal Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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- 03 Feb, 2007 3 commits
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Rafa Bilski authored
Now there is no need to depend on -1 in Nehemiah tables. After previous change code is eliminating multipliers lower then 5.0 by minmult for Nehemiah A and B. Signed-off-by: Rafa³ Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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Rafa Bilski authored
Looks like some time ago I introduced a bug to Longhaul. I had report that 9x133Mhz CPU is seen as 5x133MHz. So I changed multipliers table. That was a mistake. According to documentation table was correct. So only way to avoid 5 or 9 dilema is not use MaxMHzBR for PowerSaver 1.0. One code that works on all processors. To do it I need also separate flag for Nehemiah C (min = x4.0) and Nehemiah (min = x5.0). Signed-off-by: Rafa³ Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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Rafa Bilski authored
There is no need to have this option in Longhaul anymore. It was for laptop with CLE266 chipset in times, when only ACPI C3 was used to switch frequency. Now we have native support not only for CLE266, but CN400 too. Would be good to have support for PN266, but I can't find datasheet for it. Looks like BIOS for CPU's faster then 1GHz don't support ACPI C2 nor C3. Signed-off-by: Rafa³ Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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- 03 Jan, 2007 2 commits
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Dave Jones authored
Bunch of unused vars + one case where gcc isn't smart enough. Signed-off-by: Dave Jones <davej@redhat.com>
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Rafa Bilski authored
This is patch that solves Ebox mini PC issue and make FSB code more specification compilant. At start guess_fsb function is guessing 200MHz FSB too. It is better to make it in this way because, thanks to this function, driver will fail for bogus FSB values caused by bogus multiplier value. For PowerSaver processors we can't depend on Max / MinMHzFSB because these values are only used for PowerSaver 2.0 and 3.0. Most processors on which Longhaul is used are PowerSaver 1.0 only. I'm changing code for older CPU's too, but not so much as previously, and this code was already used for Ezra. Using MinMHzBR for Ezra-T is outside spec. It is for voltage scaling purpose and don't have to be equal to minmult (but it is). Same for Nehemiah (it isn't for sure). Added mult - current multiplier value. Signed-off-by: Rafa³ Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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- 29 Dec, 2006 2 commits
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Rafa Bilski authored
ACPI PM2 register was fallback for "Longhaul ver. 1" CPU's. My assumption that this register isn't present at "PowerSaver" motherboards is so far true, but current code will not work correctly in other case. There are three possible supports: ACPI C3, PM2 and northbridge. That was my assumption that ACPI C3 and northbridge is for PS and northbridge and PM2 is for V1. In current code we can only check if it is ACPI support or not by port22_en. So remove port22_en and add longhaul_flags. If USE_ACPI_C3 and USE_NORTHBRIDGE are both clear then it means ACPI PM2 support. Also change order of support probe from ACPI C3, PM2, northbridge to ACPI C3, northbridge, ACPI PM2. Paranoid protection against port 0x22 cast as ACPI PM2 register. Bit 1 clear in such case - lockup on AGP DMA. And obvious (now) fixup for do_powersaver. Use cx->address only for ACPI C3 ("PowerSaver" processor using PM2 support). Signed-off-by: Rafa Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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Dave Jones authored
Signed-off-by: Rafał Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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- 18 Dec, 2006 2 commits
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Dave Jones authored
Some gcc's are more anal than others about empty switch labels. error: label at end of compound statement Signed-off-by: Dave Jones <davej@redhat.com>
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Dave Jones authored
C7's are centrino speedstep-alike. Signed-off-by: Dave Jones <davej@redhat.com>
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- 12 Dec, 2006 2 commits
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Rafa Bilski authored
Support for CN400 northbridge when ACPI C3 isn't available. Tested on Epia SP13000. Thanks to Robert for testing it. Signed-off-by: Rafa Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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Rafa Bilski authored
On board of Epia SP13000 is 10x133Mhz VIA Nehemiah. It is reported as 10x200MHz. This patch is fixing this issue. Signed-off-by: Rafa Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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- 27 Sep, 2006 2 commits
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Rafa Bilski authored
removing duplicated code. Signed-off-by: Rafa Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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rafalbilski@interia.pl authored
Please ignore previous message. This patch is adding support for CPU connected to CLE266 chipset. For older CPU this is only way. For "Powersaver" processor this way will be used if ACPI C3 isn't supported. I have tested it. It seems to work exacly like ACPI. But it is less safe. On CLE266 chipset port 0x22 is blocking processor access to PCI bus too. Signed-off-by: Rafa³ Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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- 05 Sep, 2006 1 commit
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Rafa Bilski authored
Rename option "dont_scale_voltage" to "scale_voltage" because don't will be default. Use "pos" for calculating voltage. In this way driver don't need to know mV value or low level value. Simply min U is one pos and max U is second pos. All pos between these two are used. Assume that min U is for min f and max U for max f. For frequency between min and max calculate pos based on difference between current frequency and min f. Values in mobile VRM table changed to values from C3-M datasheet. Signed-off-by: Rafa³ Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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- 14 Aug, 2006 1 commit
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Rafa Bilski authored
Some laptops with VIA C3 processor, CLE266 chipset and AMI BIOS have incorrect latency values in FADT table. These laptops seems to be C3 capable, but latency values are to big: 101 for C2 and 1017 for C3. This option will allow user to skip C3 latency test but not C3 address test. AMI BIOS is setting C3 address to correct value in DSDT table. Signed-off-by: Rafa Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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- 11 Aug, 2006 1 commit
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Rafa Bilski authored
ACPI C3 works for "Powersaver" processors, so use it only for them. Older CPU will change frequency on "halt" only. But we can protect transition in two ways: - by ACPI PM2 register, there is "bus master arbiter disable" bit. This isn't tested because VIA mainboards don't have PM2 register, - by PLE133 PCI/AGP arbiter disable register. There are two bits in this register. First is "PCI arbiter disable", second "AGP arbiter disable". This is working on VIA Epia 800 mainboards. Test on bm_control is more proper because this is true when PM2 register exist. Signed-off-by: Rafa³ Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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- 31 Jul, 2006 7 commits
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Rafa Bilski authored
This table is only used by Ezra-T CPUs currently, and has values for some other CPU. Fix them to match the values used by that CPU, and for now make it clearer by renaming the variable. Signed-off-by: Rafa³ Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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Rafa Bilski authored
This is changing "always true" test to something usefull. Signed-off-by: Rafa Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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Rafa Bilski authored
I lost very important line in do_powersaver Signed-off-by: Rafa Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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Adrian Bunk authored
This patch makes the needlessly global longhaul_walk_callback() static. Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Dave Jones <davej@redhat.com>
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Rafa Bilski authored
Without this longhaul will always fail when compiled into kernel, as it needs to initialise after the ACPI processor module. I lost this when I was splitting patches. Sorry. Signed-off-by: Rafa Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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Rafa Bilski authored
There is no need to worry about local APIC. There is need to worry about I/O APIC, because I/O APIC is replacing good old 8259. According to Nehemiah datasheet VIA is using 3-wire bus to connect local APIC to I/O APIC. "[...] When IA32_APIC_BASE[11] is set to 0, processor APICs based on the 3-wire APIC bus cannot be generally re-enabled until a system hardware reset. The 3-wire bus looses track of arbitration that would be necessary for complete re-enabling. Certain (local) APIC functionality can be enabled. [...]" So we must set disable bit for each interrupt in I/O APIC registers. Same situation as for PIC - we must poke registers direcly. How to do this? I don't know. So at the moment it is better to fail. Signed-off-by: Rafa³ Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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Rafa Bilski authored
Minimal change necessary for hardware support. Changes in longhaul.c: - most important - now C3 state is causing transition, - code responsible for clearing "bus master" bit removed, - protect bcr2 transition in the same way as longhaul. Signed-off-by: Rafa³ Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
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- 30 May, 2006 2 commits
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Dave Jones authored
Signed-off-by: Dave Jones <davej@redhat.com>
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Dave Jones authored
Getting ready to move to core cpufreq. - Use snprintf - Remove unnecessary nesting improving readability. Signed-off-by: Dave Jones <davej@redhat.com>
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- 05 Sep, 2005 1 commit
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Zachary Amsden authored
i386 Inline asm cleanup. Use cr/dr accessor functions. Also, a potential bugfix. Also, some CR accessors really should be volatile. Reads from CR0 (numeric state may change in an exception handler), writes to CR4 (flipping CR4.TSD) and reads from CR2 (page fault) prevent instruction re-ordering. I did not add memory clobber to CR3 / CR4 / CR0 updates, as it was not there to begin with, and in no case should kernel memory be clobbered, except when doing a TLB flush, which already has memory clobber. I noticed that page invalidation does not have a memory clobber. I can't find a bug as a result, but there is definitely a potential for a bug here: #define __flush_tlb_single(addr) \ __asm__ __volatile__("invlpg %0": :"m" (*(char *) addr)) Signed-off-by: Zachary Amsden <zach@vmware.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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- 01 Sep, 2005 1 commit
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Dave Jones authored
From: Denis Vlasenko <vda@ilport.com.ua> Signed-off-by: Dave Jones <davej@redhat.com>
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- 01 Jun, 2005 3 commits
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Dave Jones authored
From patch by: Ken Staton <ken_staton@agilent.com> Signed-off-by: Dave Jones <davej@redhat.com>
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Dave Jones authored
As mandated by the spec, disable timer around transitions. From code by : Ken Staton <ken_staton@agilent.com Signed-off-by: Dave Jones <davej@redhat.com>
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Dave Jones authored
The spec states that we have to do this, which is *horrid*. Based on code from: Ken Staton <ken_staton@agilent.com> Signed-off-by: Dave Jones <davej@redhat.com>
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- 16 Apr, 2005 1 commit
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Linus Torvalds authored
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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