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  1. 11 Feb, 2007 2 commits
  2. 04 Feb, 2007 2 commits
    • Rafa Bilski's avatar
      [CPUFREQ] Longhaul - Add VT8235 support · 786f46b2
      Rafa Bilski authored
      I don't know why it is working and how, but it is working. On my
      Epia transition time is by default set to 100us. I'm changing it to
      200us. After that I can change frequency from min (x4.0) to max (x7.5)
      without lockup. Many times.
      There is a paranoid check at a beginning of a patch. Probably dead
      code, but I don't have better ideas for CL10000 case at the moment.
      Only way to to detect broken chip seems to be looking in log for
      spurious interrupts.
      Signed-off-by: default avatarRafal Bilski <rafalbilski@interia.pl>
      Signed-off-by: default avatarDave Jones <davej@redhat.com>
      786f46b2
    • Rafa Bilski's avatar
      [CPUFREQ] Longhaul - Fix guess_fsb function · 46ef955f
      Rafa Bilski authored
      This is bug reported by John-Marc Chandonia:
      > Detected 1002.292 MHz processor.
      > longhaul: VIA C3 'Nehemiah B' [C5N] CPU detected.  Powersaver supported.
      > longhaul: Using throttling support.
      > longhaul: Invalid (reserved) FSB!
      FSB is correcly guessed for 999.554 MHz CPU.
      To fix this error:
      - ROUNDING should be range, not mask - at it's current value it is +7 -8,
      - more precise calculations inside guess_fsb - 7.5x133MHz is 1000MHz now.
      Signed-off-by: default avatarRafal Bilski <rafalbilski@interia.pl>
      Signed-off-by: default avatarDave Jones <davej@redhat.com>
      46ef955f
  3. 03 Feb, 2007 3 commits
  4. 03 Jan, 2007 2 commits
    • Dave Jones's avatar
      [CPUFREQ] longhaul: Kill off warnings introduced by recent changes. · 43c8f12f
      Dave Jones authored
      Bunch of unused vars + one case where gcc isn't smart enough.
      Signed-off-by: default avatarDave Jones <davej@redhat.com>
      43c8f12f
    • Rafa Bilski's avatar
      [CPUFREQ] Longhaul - Always guess FSB · 24ebead8
      Rafa Bilski authored
      This is patch that solves Ebox mini PC issue and make
      FSB code more specification compilant. At start guess_fsb
      function is guessing 200MHz FSB too. It is better to
      make it in this way because, thanks to this function, driver
      will fail for bogus FSB values caused by bogus multiplier
      value. For PowerSaver processors we can't depend on Max /
      MinMHzFSB because these values are only used for
      PowerSaver 2.0 and 3.0. Most processors on which Longhaul
      is used are PowerSaver 1.0 only. I'm changing code for older
      CPU's too, but not so much as previously, and this code was
      already used for Ezra. Using MinMHzBR for Ezra-T is outside
      spec. It is for voltage scaling purpose and don't have to
      be equal to minmult (but it is). Same for Nehemiah (it
      isn't for sure). Added mult - current multiplier value.
      Signed-off-by: default avatarRafa³ Bilski <rafalbilski@interia.pl>
      Signed-off-by: default avatarDave Jones <davej@redhat.com>
      24ebead8
  5. 29 Dec, 2006 2 commits
    • Rafa Bilski's avatar
      [CPUFREQ] Longhaul - Fix up powersaver assumptions. · 264166e6
      Rafa Bilski authored
      ACPI PM2 register was fallback for "Longhaul ver. 1" CPU's.
      My assumption that this register isn't present at
      "PowerSaver" motherboards is so far true, but current code
      will not work correctly in other case. There are three possible
      supports: ACPI C3, PM2 and northbridge. That was my assumption
      that ACPI C3 and northbridge is for PS and northbridge and PM2
      is for V1. In current code we can only check if it is ACPI
      support or not by port22_en. So remove port22_en and add
      longhaul_flags. If USE_ACPI_C3 and USE_NORTHBRIDGE are both
      clear then it means ACPI PM2 support. Also change order of
      support probe from ACPI C3, PM2, northbridge to ACPI C3,
      northbridge, ACPI PM2. Paranoid protection against port 0x22
      cast as ACPI PM2 register. Bit 1 clear in such case - lockup
      on AGP DMA. And obvious (now) fixup for do_powersaver. Use
      cx->address only for ACPI C3 ("PowerSaver" processor using
      PM2 support).
      Signed-off-by: default avatarRafa Bilski <rafalbilski@interia.pl>
      Signed-off-by: default avatarDave Jones <davej@redhat.com>
      264166e6
    • Dave Jones's avatar
      1cfe2014
  6. 18 Dec, 2006 2 commits
  7. 12 Dec, 2006 2 commits
  8. 27 Sep, 2006 2 commits
  9. 05 Sep, 2006 1 commit
    • Rafa Bilski's avatar
      [CPUFREQ] Longhaul - Add voltage scaling to driver · db44aaf3
      Rafa Bilski authored
      Rename option "dont_scale_voltage" to "scale_voltage" because
      don't will be default.
      Use "pos" for calculating voltage. In this way driver don't need
      to know mV value or low level value. Simply min U is one pos and
      max U is second pos. All pos between these two are used.
      Assume that min U is for min f and max U for max f. For frequency
      between min and max calculate pos based on difference between
      current frequency and min f.
      Values in mobile VRM table changed to values from
      C3-M datasheet.
      Signed-off-by: default avatarRafa³ Bilski <rafalbilski@interia.pl>
      Signed-off-by: default avatarDave Jones <davej@redhat.com>
      db44aaf3
  10. 14 Aug, 2006 1 commit
  11. 11 Aug, 2006 1 commit
    • Rafa Bilski's avatar
      [CPUFREQ] Longhaul - Disable arbiter · 179da8e6
      Rafa Bilski authored
      ACPI C3 works for "Powersaver" processors, so use it only for them.
      
      Older CPU will change frequency on "halt" only. But we can protect transition
      in two ways:
      - by ACPI PM2 register, there is "bus master arbiter disable" bit.
        This isn't tested because VIA mainboards don't have PM2 register,
      - by PLE133 PCI/AGP arbiter disable register.
        There are two bits in this register. First is "PCI arbiter disable",
        second "AGP arbiter disable". This is working on VIA Epia 800 mainboards.
      
      Test on bm_control is more proper because this is true
      when PM2 register exist.
      Signed-off-by: default avatarRafa³ Bilski <rafalbilski@interia.pl>
      Signed-off-by: default avatarDave Jones <davej@redhat.com>
      179da8e6
  12. 31 Jul, 2006 7 commits
  13. 30 May, 2006 2 commits
  14. 05 Sep, 2005 1 commit
    • Zachary Amsden's avatar
      [PATCH] i386: inline asm cleanup · 4bb0d3ec
      Zachary Amsden authored
      i386 Inline asm cleanup.  Use cr/dr accessor functions.
      
      Also, a potential bugfix.  Also, some CR accessors really should be volatile.
      Reads from CR0 (numeric state may change in an exception handler), writes to
      CR4 (flipping CR4.TSD) and reads from CR2 (page fault) prevent instruction
      re-ordering.  I did not add memory clobber to CR3 / CR4 / CR0 updates, as it
      was not there to begin with, and in no case should kernel memory be clobbered,
      except when doing a TLB flush, which already has memory clobber.
      
      I noticed that page invalidation does not have a memory clobber.  I can't find
      a bug as a result, but there is definitely a potential for a bug here:
      
      #define __flush_tlb_single(addr) \
      	__asm__ __volatile__("invlpg %0": :"m" (*(char *) addr))
      Signed-off-by: default avatarZachary Amsden <zach@vmware.com>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      4bb0d3ec
  15. 01 Sep, 2005 1 commit
  16. 01 Jun, 2005 3 commits
  17. 16 Apr, 2005 1 commit
    • Linus Torvalds's avatar
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds authored
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4