- 13 May, 2024 40 commits
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Jesse Zhang authored
Filter invalid aca error types before performing a shift operation. Signed-off-by:
Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jesse Zhang authored
if ras_manager obj null, don't print NBIO err data Signed-off-by:
Tim Huang <Tim.Huang@amd.com> Reviewed-by:
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Jesse Zhang authored
Execution cannot reach this statement: case POWER_STATE_TYPE_BALAN. Signed-off-by:
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Jesse Zhang authored
This code cannot be reached: return "UNKNOWN";. Signed-off-by:
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Jesse Zhang authored
This less-than-zero comparison of an unsigned value is never true. feature < 0U Signed-off-by:
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Jesse Zhang authored
This less-than-zero comparison of an unsigned value is never true. type < 0U Signed-off-by:
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Jesse Zhang authored
The same code is executed when the condition err is true or false, because the code in the if-then branch and after the if statement is identical Signed-off-by:
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Jesse Zhang authored
The switch governing value clk_type cannot be SMU_GFXCLK and SMU_SCLK. Fixes: ca55f459 ("drm/amd/pm: add the fine grain tuning function for Renoir") Signed-off-by:
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Jesse Zhang authored
This code cannot be reached: return sysfs_emit(buf, "UNK....) Signed-off-by:
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Jesse Zhang authored
Set smu work laod mask may fail, so check return. Signed-off-by:
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Jesse Zhang authored
Check for specific indexes that may be invalid values. Signed-off-by:
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Jesse Zhang authored
Set smu work laod mask may fail, so check return. Signed-off-by:
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Jesse Zhang authored
Set smu work laod mask may fail, so check return. Signed-off-by:
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Jesse Zhang authored
Check for specific indexes that may be invalid values. Signed-off-by:
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Jesse Zhang authored
check ring allocate success before emit preempt ib Signed-off-by:
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Jesse Zhang authored
This greater-than-or-equal-to-zero comparison of an unsigned value is always true. fpriv->xcp_id >= 0U Signed-off-by:
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Jesse Zhang authored
Check the amdgpu_hive_info *hive that maybe is NULL. Signed-off-by:
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Jesse Zhang authored
check the pointer hive before use. Signed-off-by:
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Jesse Zhang authored
For invalid clk types, return -EINVAL to check the return. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
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Ma Jun authored
Drop redundant setting code for pcie.lanes. It overwrites the value get from pptable Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Acked-by: Yang Wang<kevinyang.wang@amd.com> Signed-off-by:
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Ma Jun authored
Fix code alignment issue Signed-off-by:
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Jesse Zhang authored
For invalid clk types, return -EINVAL to check the return. Signed-off-by:
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Jesse Zhang authored
Checks the partition mode and returns an error for an invalid mode. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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Alex Hung authored
This reverts commit c49e44ed. This causes regression on DP link layer test. Reported-by:
Mark Broadworth <Mark.Broadworth@amd.com> Acked-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
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Mukul Joshi authored
We are incorrectly passing the first XCC's MQD when updating CU masks for other XCCs in the partition. Fix this by passing the MQD for the XCC currently being updated with CU mask to update_cu_mask function. Fixes: fc6efed2 ("drm/amdkfd: Update CU masking for GFX 9.4.3") Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - Read default boot options - Find max flickerless instant vtotal delta - Refactor dcn401_update_clocks - Reduce I2C speed to 95kHz in DCN401 - Allow higher DSC slice support for small timings on dcn401 - Don't offload flip if not only address update - Check UHBR13.5 cap when determining max link cap - Enable SYMCLK gating in DCCG - Expand to higher link rates - Add left edge pixel for YCbCr422/420 + ODM pipe split - Add resource interfaces for get ODM slice rect - Add COEF filter types for DCN401 - Refactor DCN401 DCCG into component directory - Fix 3dlut size for Fastloading on DCN401 - Fix write to non-existent reg on DCN401 - Remove USBC check for DCN32 - Remove unused code for some dc files - Disable AC/DC codepath when unnecessary - Create dcn401_clk_mgr struct Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Duncan Ma authored
[WHY] DPIA boot option is set by VBIOS. It gets overwritten when driver loads DMU. [HOW] Read PreOS boot options and determine if dpia is enabled. Reviewed-by:
Ovidiu Bunea <ovidiu.bunea@amd.com> Acked-by:
Duncan Ma <duncan.ma@amd.com> Tested-by:
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Ethan Bitnun authored
[WHAT & HOW] - Populate dml 2 callback with get_max_flickerless_instant_vtotal_increase - Use long long when necessary to prevent overflow - Add asic specific default values, currently disabled by default for every asic - Use the pre-existing debug option to protect the call to get_max_flickerless_instant_vtotal_increase Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Ethan Bitnun <etbitnun@amd.com> Tested-by:
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Dillon Varone authored
[WHY & HOW] Refactor complex code into manageable functions. This also cleans up some updating logics. Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Tested-by:
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Chris Park authored
[WHY] HW for DCN401 is presented with a small I2C speed fluctuation that exceeds the hard cap limitation of 100kHz occasionally. This violates compliance requirement and will result in failure in compliance. [HOW] After various measurements and traceback to previous generation HW, DCN IP, SI and SW driver agrees that we can reduce I2C speed to 95kHz to address the I2C spped fluctuation in DCN401. Reviewed-by:
Chris Park <chris.park@amd.com> Tested-by:
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Wenjing Liu authored
[WHY] DML2.1 has added the support to determine ODM combine based on DSC slice count limitation. This support would allow us to support DSC slice higher than 4 on small timings. The change will allow higher DSC slice support independent from pixel clock in use. [HOW] Add a DCN401 get_enc_caps function to allow the support for DSC slice count higher than 4. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Alvin Lee authored
[WHAT & HOW] Fast updates can consist of some stream updates as well (i.e., out_csc). In these cases we should not offload the flip to FW as we can only offload address only updates to FW. Reviewed-by:
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George Shen authored
[WHY] UHBR13.5 support is optional, even if UHBR20 is supported by the device. If source supports max UHBR13.5 while sink, cable and LTTPR support UHBR20 but not UHBR13.5, UHBR10 should be used as the max link cap. Reviewed-by:
George Shen <george.shen@amd.com> Tested-by:
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Daniel Miess authored
[WHY & HOW] Enable root clock optimization for SYMCLK and only disable it when it's actively used. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Daniel Miess <daniel.miess@amd.com> Tested-by:
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Sung Joon Kim authored
[WHY & HOW] To support higher link rates that sink allows, we need to make sure driver is ready and perform correct link-training sequence. Reviewed-by:
Sung Joon Kim <sungjoon.kim@amd.com> Tested-by:
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Wenjing Liu authored
[WHY] Currently 3-tap chroma subsampling is used for YCbCr422/420. When ODM pipesplit is used, pixels on the left edge of ODM slices need one extra pixel from the right edge of the previous slice to calculate the correct chroma value. Without this change, the chroma value is slightly different than expected. This is usually imperceptible visually, but it impacts test pattern CRCs for compliance test automation. [HOW] Update logic to use the register for adding extra left edge pixel for YCbCr422/420 ODM cases. Reviewed-by:
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Wenjing Liu authored
[WHY] We need an unified location to perform ODM slice rect calculation. [HOW] Add three interfaces for ODM slice rect/width calucaltion in resource.h Reviewed-by:
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Samson Tam authored
Add VERTICAL_BLUR_SCALE & HORIZONTAL_BLUR_SCALE types. Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Samson Tam <samson.tam@amd.com> Tested-by:
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Revalla Hari Krishna authored
[WHY] Clean up the code that requires dccg to be in its own component. [HOW] Move all files under newly created dccg dir and fix the makefiles. Acked-by:
Revalla Hari Krishna <Harikrishna.Revalla@amd.com> Tested-by:
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Adam Nelson authored
[WHY] After a non-3dlut test the MPCC_MCM_3DLUT_MODE::MPCC_MCM_3DLUT_SIZE is incorrect. [HOW] Add register write to make valid. Acked-by:
Adam Nelson <adnelson@amd.com> Tested-by:
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