- 27 Apr, 2011 12 commits
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Michael Ellerman authored
If we don't find ibm,associativity-reference-points as a child of /rtas, look for it at the root of the tree instead. We use this on Book3E where we have no RTAS but still use the sPAPR conventions for NUMA. Signed-off-by:
Michael Ellerman <michael@ellerman.id.au> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Michael Ellerman authored
Even when no initfunc is provided. Signed-off-by:
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Michael Ellerman authored
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Michael Ellerman authored
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Michael Ellerman authored
The goal is to avoid adding overhead to MMIO when only PIO is needed Signed-off-by:
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Nishanth Aravamudan authored
Commit fe3cc0d9 ("powerpc: Add pgprot_writecombine") in benh's tree exposes the pgprot_writecombine() API to drivers on powerpc. cxgb4 has an open-coded version of the same, so use the common API now that it's available. Signed-off-by:
Nishanth Aravamudan <nacc@us.ibm.com> Cc: Steve Wise <swise@opengridcomputing.com> Cc: Anton Blanchard <anton@samba.org> Acked-by:
Steve Wise <swise@opengridcomputing.com> Signed-off-by:
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Alexey Kardashevskiy authored
The DSCR (aka Data Stream Control Register) is supported on some server PowerPC chips and allow some control over the prefetch of data streams. This patch allows the value to be specified per thread by emulating the corresponding mfspr and mtspr instructions. Children of such threads inherit the value. Other threads use a default value that can be specified in sysfs - /sys/devices/system/cpu/dscr_default. If a thread starts with non default value in the sysfs entry, all children threads inherit this non default value even if the sysfs value is changed later. Signed-off-by:
Alexey Kardashevskiy <aik@au1.ibm.com> Signed-off-by:
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Jack Miller authored
When we set up the TLB for ourselves on Book3E, we need to flush out any old mappings established by the firmware or bootloader. At present we attempt this with a tlbilx to flush everything, but this will leave behind any entries with the IPROT bit set. There are several good reason firmware might establish mappings with IPROT, and in fact ePAPR compliant firmwares are required to establish their initial mapped area with IPROT. This patch, therefore adds more complex code to scan through the TLB upon entry and flush away any entries that are not our own. Signed-off-by:
Jack Miller <jack@codezen.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au> Signed-off-by:
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Benjamin Herrenschmidt authored
An erratum on A2 can lead to the bolted entry we insert for the linear mapping being evicted, to avoid that write the bolted entry to way 3. Signed-off-by:
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Michael Ellerman authored
In exc_lvl_ctx_init() we index into the crit/dbg/mcheck stacks using the hard cpu id, but that assumes the hard cpu id is zero based and contiguous. That is not the case on A2. The root of the problem is that the 32bit code has no equivalent of the paca to allow it to do the hard->soft mapping in assembler. Until the 32bit code is updated to handle that, index the stacks using the soft cpu ids on 64bit and hard on 32 bit. Signed-off-by:
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Benjamin Herrenschmidt authored
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Benjamin Herrenschmidt authored
Add the cputable entry, regs and setup & restore entries for the PowerPC A2 core. Signed-off-by:
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- 20 Apr, 2011 28 commits
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Benjamin Herrenschmidt authored
As well as searching for nodes with type = "nvram", search for nodes that have compatible = "nvram". This can't be converted into a single call to of_find_compatible_node() with a non-NULL type, because that searches for a node that has _both_ type & compatible = "nvram". Signed-off-by:
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Michael Ellerman authored
An upcoming new ics backend will need to implement different matching semantics to the current ones, which are essentially the RTAS ics backends. So move the current match into the RTAS backend, and allow other ics backends to override. Signed-off-by:
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Benjamin Herrenschmidt authored
SCOM is a side-band configuration bus implemented on some processors. This code provides a way for code to map and operate on devices via SCOM, while the details of how that is implemented is left up to a SCOM "controller" in the platform code. Signed-off-by:
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Michael Ellerman authored
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Michael Ellerman authored
We have platform code that needs to find a node's interrupt parent, so export of_irq_find_parent() so we can use it. Signed-off-by:
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Benjamin Herrenschmidt authored
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Anton Blanchard authored
There are a few places we patch instructions without using patch_instruction and patch_branch, probably because they predated it. Fix it. Signed-off-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
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Michael Ellerman authored
Currently we allocate the stale_map for a cpu when it comes online, this leaves open a small window where a process can be scheduled on the cpu before the stale_map is allocated. Instead allocate the stale_map at CPU_UP_PREPARE time, that way it will be always available before tasks start running. It is possible the cpu fails to come up, in which case we should free the stale_map, so add a CPU_UP_CANCELED case to do that. Signed-off-by:
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Michael Ellerman authored
When we start a cpu we use smp_ops->kick_cpu(), which currently returns void, it should be able to fail. Convert it to return int, and update all uses. Convert all the current error cases to return -ENOENT, which is what would eventually be returned by __cpu_up() currently when it doesn't detect the cpu as coming up in time. Signed-off-by:
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David Gibson authored
This is a first cut at making bootwrapper code which will produce a zImage compliant with the requirements set down by ePAPR. This is a very simple bootwrapper, taking the device tree blob supplied by the ePAPR boot program and passing it on to the kernel. It builds on the earlier patch to build a relocatable ET_DYN zImage to meet the other ePAPR image requirements. For good measure we have some paranoid checks which will generate warnings if some of the ePAPR entry condition guarantees are not met. Signed-off-by:
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Michael Ellerman authored
This patch adds code, linker script and makefile support to allow building the zImage wrapper around the kernel as a position independent executable. This results in an ET_DYN instead of an ET_EXEC ELF output file, which can be loaded at any location by the firmware and will process its own relocations to work correctly at the loaded address. This is of interest particularly since the standard ePAPR image format must be an ET_DYN (although this patch alone is not sufficient to produce a fully ePAPR compliant boot image). Note for now we don't enable building with -pie for anything. Signed-off-by:
Paul Mackerras <paulus@samba.org> Signed-off-by:
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Michael Ellerman authored
On Book3E, MMU_NO_CONTEXT != 0, but the slice_mm_new_context() macro assumes that it is. This means that the map of the page sizes for each slice is always initialized to zeroes (which happens to be 4k pages), rather than to the correct default base page size value - which might be 64k. This patch corrects the problem. Signed-off-by:
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Michael Ellerman authored
Use MMU_NO_CONTEXT as the initialiser for mm_context.id on nohash and hash64. Signed-off-by:
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Benjamin Herrenschmidt authored
Adds the ability to print decimal numbers and adds some more format string variants Signed-off-by: -
Benjamin Herrenschmidt authored
We need to do that to guarantee they see any code change done by dynamic patching during boot. Signed-off-by: -
Benjamin Herrenschmidt authored
Wakeup comes from the system reset handler with a potential loss of the non-hypervisor CPU state. We save the non-volatile state on the stack and a pointer to it in the PACA, which the system reset handler uses to restore things Signed-off-by: -
Benjamin Herrenschmidt authored
We need to wait a bit for them to have done their CPU setup or we might end up with translation and EE on with different LPCR values between threads Signed-off-by: -
Benjamin Herrenschmidt authored
We do it before we loop on the PACA start flag. This way, we get a chance to set critical SPRs on all CPUs before Linux tries to start them up, which avoids problems when changing some bits such as LPCR bits that need to be identical on all threads of a core or similar things like that. Ideally, some of that should also be done before the MMU is enabled, but that's a separate issue which would require moving some of the SMP startup code earlier, let's not get there for now, it works with that change alone. Signed-off-by: -
Benjamin Herrenschmidt authored
In case entry from the bootloader isn't "clean" Signed-off-by: -
Benjamin Herrenschmidt authored
This sets the default data stream prefetch size for operating systems that don't set their own value in DSCR. We use 4 which is "medium". Signed-off-by: -
Paul Mackerras authored
This uses feature sections to arrange that we always use HSPRG1 as the scratch register in the interrupt entry code rather than SPRG2 when we're running in hypervisor mode on POWER7. This will ensure that we don't trash the guest's SPRG2 when we are running KVM guests. To simplify the code, we define GET_SCRATCH0() and SET_SCRATCH0() macros like the GET_PACA/SET_PACA macros. Signed-off-by:
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Benjamin Herrenschmidt authored
Rework exception macros a bit to split offset from vector and add some basic support for HDEC, HDSI, HISI and a few more. Signed-off-by: -
Benjamin Herrenschmidt authored
Pass the register type to the prolog, also provides alternate "HV" version of hardware interrupt (0x500) and adjust LPES accordingly We tag those interrupts by setting bit 0x2 in the trap number Signed-off-by: -
Benjamin Herrenschmidt authored
When running in Hypervisor mode (arch 2.06 or later), we store the PACA in HSPRG0 instead of SPRG1. The architecture specifies that SPRGs may be lost during a "nap" power management operation (though they aren't currently on POWER7) and this enables use of SPRG1 by KVM guests. Signed-off-by: -
Benjamin Herrenschmidt authored
This bit indicates that we are operating in hypervisor mode on a CPU compliant to architecture 2.06 or later (currently server only). We set it on POWER7 and have a boot-time CPU setup function that clears it if MSR:HV isn't set (booting under a hypervisor). Signed-off-by: -
Benjamin Herrenschmidt authored
Even when nothing is specified in the device tree, and despite the fact that we don't setup links properly yet, we still need a reasonable value in there or some interrupts won't be setup properly to point to an existing processor. Signed-off-by: -
Benjamin Herrenschmidt authored
This adds more SPR definitions used on newer processors when running in hypervisor mode. Along with some other P7 specific bits and pieces Signed-off-by: -
Benjamin Herrenschmidt authored
This is a significant rework of the XICS driver, too significant to conveniently break it up into a series of smaller patches to be honest. The driver is moved to a more generic location to allow new platforms to use it, and is broken up into separate ICP and ICS "backends". For now we have the native and "hypervisor" ICP backends and one common RTAS ICS backend. The driver supports one ICP backend instanciation, and many ICS ones, in order to accomodate future platforms with multiple possibly different interrupt "sources" mechanisms. Signed-off-by:
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