- 12 May, 2019 1 commit
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Mark Brown authored
Merge tag 'spi-bpw-is-supported' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-5.3 spi: Add spi_is_bpw_supported() Lets client drivers check and potentially handle issues.
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- 08 May, 2019 11 commits
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Emil Renner Berthing authored
This fixes tx and bi-directional dma transfers on rk3399-gru-kevin. It seems the SPI fifo must have room for 2 bursts when the dma_tx_req signal is generated or it might skip some words. This in turn makes the rx dma channel never complete for bi-directional transfers. Fix it by setting tx burst length to fifo_len / 4 and the dma watermark to fifo_len / 2. However the rk3399 TRM says (sic): "DMAC support incrementing-address burst and fixed-address burst. But in the case of access SPI and UART at byte or halfword size, DMAC only support fixed-address burst and the address must be aligned to word." So this relies on fifo_len being a multiple of 16 such that the burst length (= fifo_len / 4) is a multiple of 4 and the addresses will be word-aligned. Fixes: dcfc861d ("spi: rockchip: adjust dma watermark and burstlen") Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Mark Brown <broonie@kernel.org>
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Martin Sperl authored
Support setting a delay between cs assert and deassert as a multiple of spi clock length. Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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Martin Sperl authored
For some SPI devices that support speed_hz > 1MHz the default 10 us delay when cs_change = 1 is typically way to long and may result in poor spi bus utilization. This patch makes it possible to control the delay at micro or nano second resolution on a per spi_transfer basis. It even allows an "as fast as possible" mode with: xfer.cs_change_delay_unit = SPI_DELAY_UNIT_NSECS; xfer.cs_change_delay = 0; The delay code is shared between delay_usecs and cs_change_delay for consistency and reuse, so in the future this change_delay_unit could also apply to delay_usec as well. Note that on slower SOCs/CPU actually reaching ns deasserts on cs is not realistic as the gpio overhead alone (without any delays added ) may already leave cs deasserted for more than 1us - at least on a raspberry pi. But at the very least this way we can keep it as short as possible. Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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Martin Sperl authored
To estimate efficiency add statistics on transfer types (polling, interrupt and dma) used to debugfs. Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Changelog: V1 -> V2: applied feedback by Stefan Wahren reorganized patchset added extra rational, descriptions fixed compile issue when CONFIG_DEBUG_FS is unset Signed-off-by: Mark Brown <broonie@kernel.org>
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Martin Sperl authored
Under some circumstances the default 30 us polling limit is not optimal and may lead to long delays because we are waiting on an interrupt. with this patch we have the possibility to influence this policy. So make this limit (in us) configurable via a module parameters (but also modifyable via /sys/modules/...) This replicates similar code found in spi-bcm2835aux. Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Changelog: V1 -> V2: applied feedback by Stefan Wahren reorganized patchset added extra rational, descriptions Signed-off-by: Mark Brown <broonie@kernel.org>
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Martin Sperl authored
The DMA mode behaves slightly different than polling or interrupt driven mode, so just document the fact Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Changelog: V1 -> V2: applied feedback by Stefan Wahren new in V2 Signed-off-by: Mark Brown <broonie@kernel.org>
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Martin Sperl authored
Avoid 64 bit aritmetics when deciding if we need to use polling or not This replicates: commit d704afff ("spi: bcm2835aux: Avoid 64-bit arithmetic in xfer len calc") from spi-bcm2835aux Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Changelog: V1 -> V2: applied feedback by Stefan Wahren reorganized patchset added extra rational, descriptions Signed-off-by: Mark Brown <broonie@kernel.org>
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Martin Sperl authored
Remove the unnecessary argument of xfer_time_us when calling bcm2835_spi_transfer_one_poll. Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Changelog: V1 -> V2: applied feedback by Stefan Wahren reorganized patchset added extra rational, descriptions Signed-off-by: Mark Brown <broonie@kernel.org>
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Radu Pirea authored
This patch adds support for DMA. Transfers are done with dma only if they are longer than 16 bytes in order to achieve a better performance. DMA setup introduces a little overhead and for transfers shorter than 16 bytes there is no performance improvement. Signed-off-by: Radu Pirea <radu_nicolae.pirea@upb.ro> Signed-off-by: Mark Brown <broonie@kernel.org>
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Radu Pirea authored
The bindings for DMA are now common for both drivers of the USART IP. The node given as an example for USART in SPI mode has been updated in order to include DMA bindings. Signed-off-by: Radu Pirea <radu_nicolae.pirea@upb.ro> Signed-off-by: Mark Brown <broonie@kernel.org>
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Linus Walleij authored
My previous patch leaves a dangling variable in the driver. get rid of it. Fixes: 06a391b1621e ("spi: ep93xx: Convert to use CS GPIO descriptors") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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- 02 May, 2019 24 commits
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Mark Brown authored
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Mark Brown authored
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Hoan Nguyen An authored
Process handling QSPI when transmit/receive at qspi_trigger_transfer_out_in() as follows: Setting the trigger, is the number of bytes in the FIFO buffer to determine when there is an interrupt. Then check if the value of triggering number is 32-bytes or 1-byte, there will be corresponding processing Handling (if (n == QSPI_BUFFER_SIZE) esle) this is unnecessary, leads to the same processing of data transmission or reception, The difference here are with ret = rspi_wait_for_tx_empty(rspi); ret = rspi_wait_for_rx_full(rspi); When the nummber trigger is 32 bytes, we only write into FIFO when the FIFO is completely empty (interrupt transmission), and only receive if FIFO is full of 32 bytes of data. In the case of a nummber trigger that is 1 byte, in principle we still need to process rspi_wait_for_tx_empty/full so that FIFO is empty only with the amount of data we need to write to or equal to the number of bytes we need to receive, There is currently no processing of this. And in the current case with this patch, at this time it only needs at least 1 byte received in FIFO that has interrupt received, or FIFO at least 1bytes free can be written into FIFO, This patch therefore does not affect this processing. So we need to eliminate unnecessary waste processing (if (n == QSPI_BUFFER_SIZE) esle), more precisely in waiting for FIFO status. The same with handling in qspi_transfer_out()/qspi_transfer_in(). Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp> Signed-off-by: Mark Brown <broonie@kernel.org>
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Claudiu Beznea authored
atmel_qspi objects are kept in spi_controller objects, so, first get pointer to spi_controller object and then get atmel_qspi object from spi_controller object. Fixes: 2d30ac5e ("mtd: spi-nor: atmel-quadspi: Use spi-mem interface for atmel-quadspi driver") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Fabien Dessenne authored
During probe, return the "get_irq" error value instead of -ENOENT. This allows the driver to be defer probed if needed. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Sowjanya Komatineni authored
This patch fixes PIO mode transfer to use PIO bit in SPI_COMMAND1 register. Current driver uses DMA_EN instead of PIO bit. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Flavio Suligoi authored
Calculate the divisor for the SCR (Serial Clock Rate), avoiding that the SSP transmission rate can be greater than the device rate. When the division between the SSP clock and the device rate generates a reminder, we have to increment by one the divisor. In this way the resulting SSP clock will never be greater than the device SPI max frequency. For example, with: - ssp_clk = 50 MHz - dev freq = 15 MHz without this patch the SSP clock will be greater than 15 MHz: - 25 MHz for PXA25x_SSP and CE4100_SSP - 16,56 MHz for the others Instead, with this patch, we have in both case an SSP clock of 12.5MHz, so the max rate of the SPI device clock is respected. Signed-off-by: Flavio Suligoi <f.suligoi@asem.it> Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Serge Semin authored
When GPIO chip-select is used nothing prevents any available SPI controllers to work with both CS-high and traditional CS-low modes. In fact the SPI bus core code already does it, so we don't need to introduce any modification there. But spi_setup() still fails to switch the interface settings if CS-high flag is set for the case of GPIO-driven slave chip-select when the SPI controller doesn't support the hardwired CS-inversion. Lets fix it by clearing the SPI_CS_HIGH flag out from bad_bits (unsupported by controller) when client chip is selected by GPIO. This feature is useful for slave devices, which in accordance with communication protocol can work with both active-high and active-low chip-selects. I am aware of one such device. It is MMC-SPI interface, when at init sequence the driver needs to perform a read operation with low and high chip-select sequentially (requirement of 74 clock cycles with both chipselect, see the mmc_spi driver for details). Signed-off-by: Serge Semin <fancer.lancer@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Linus Walleij authored
This converts the EP93xx SPI master driver to use GPIO descriptors for chip select handling. EP93xx was using platform data to pass in GPIO lines, by converting all board files to use GPIO descriptor tables the core will look up the GPIO lines from the SPI device in the same manner as for device tree. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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Daniel Gomez authored
Add missing <of_device_id> table for SPI driver relying on SPI device match since compatible is in a DT binding or in a DTS. Before this patch: modinfo sound/soc/codecs/snd-soc-adau1977-spi.ko | grep alias alias: spi:adau1979 alias: spi:adau1978 alias: spi:adau1977 After this patch: modinfo sound/soc/codecs/snd-soc-adau1977-spi.ko | grep alias alias: of:N*T*Cadi,adau1979C* alias: of:N*T*Cadi,adau1979 alias: of:N*T*Cadi,adau1978C* alias: of:N*T*Cadi,adau1978 alias: of:N*T*Cadi,adau1977C* alias: of:N*T*Cadi,adau1977 alias: spi:adau1979 alias: spi:adau1978 alias: spi:adau1977 Reported-by: Javier Martinez Canillas <javier@dowhile0.org> Signed-off-by: Daniel Gomez <dagmcr@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Naga Sureshkumar Relli authored
Alpha and some of the architectures are missing readsl/writesl functions. so the zynq-qspi driver won't be able to build on these arches. hence use ioread32_rep()/iowrite32_rep() instead of readsl()/writesl(). Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Fabien Dessenne authored
During probe, check the "get_irq" error value. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Meghana Madhyastha authored
Split spi transfers into chunks of <=65532 to enable the driver to perform DMA transfer on big buffers. The DLEN register specifies the number of bytes to transfer in DMA mode. It is 16-bit wide and thus the maximum DMA transfer is 65535 bytes. Set the maximum to 65532 (4 byte aligned) since the FIFO in DMA mode is accessed in 4 byte chunks. ->max_dma_len is the value the spi core uses when splitting the buffer into scatter gather entries. The BCM2835 DMA block has 2 types of channels/engines: - Normal: Max length: 1G - Lite: Max length: 65535 Even when using a Lite channel we will not exceed the max length, so let's drop setting ->max_dma_len. Signed-off-by: Meghana Madhyastha <meghana.madhyastha@gmail.com> Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Mark Brown <broonie@kernel.org>
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Sowjanya Komatineni authored
This patch changes mode and mode_bits from u16 to u32 to allow more mode configurations. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Leilk Liu authored
Add binding documentation of spi-mt65xx for MT8516 SOC. Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Evan Green authored
Add PCI IDs for SPI on Comet Lake. Signed-off-by: Evan Green <evgreen@chromium.org> Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Noralf Trønnes authored
Large transfers (64kB) doesn't show up in the trace. Not sure why, but since printk can only display buffers up to 64 bytes in length, we only need to store the first 64 bytes. Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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Noralf Trønnes authored
spi_split_transfers_maxsize() can be used to split a transfer. This function uses spi_res to lifetime manage the added transfer structures. So in order to finalize the current message while it contains the split transfers, spi_res_release() must be called after finalizing. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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Noralf Trønnes authored
Don't warn about splitting transfers, the info is available in the statistics if needed. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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Jarkko Nikula authored
Falling back to maximum speed of the controller in case of SPI slave maximum speed is not set is needless. It already defaults to maximum speed of the controller since commit 052eb2d4 ("spi: core: Set max_speed_hz of spi_device default to max_speed_hz of controller"). Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Cao Van Dong authored
Document SoC specific bindings for R-Car RZ/G1C(r8a77470) SoC. Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Signed-off-by: Mark Brown <broonie@kernel.org>
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Flavio Suligoi authored
With dw_dmac, sometimes the request of a DMA channel fails because the DMA driver is not ready, so an explicit dependency request is necessary. Signed-off-by: Flavio Suligoi <f.suligoi@asem.it> Signed-off-by: Mark Brown <broonie@kernel.org>
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YueHaibing authored
Stub helper spi_mem_default_supports_op() should be set to static inline Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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YueHaibing authored
When building with CONFIG_SPI_MEM is not set gc warns this: drivers/spi/spi-zynq-qspi.o: In function `zynq_qspi_supports_op': spi-zynq-qspi.c:(.text+0x1da): undefined reference to `spi_mem_default_supports_op' Fixes: 67dca5e5 ("spi: spi-mem: Add support for Zynq QSPI controller") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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- 29 Apr, 2019 1 commit
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Linus Torvalds authored
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- 28 Apr, 2019 3 commits
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git://git.armlinux.org.uk/~rmk/linux-armLinus Torvalds authored
Pull ARM fixes from Russell King: "A small number of ARM fixes - Fix function tracer and unwinder dependencies so that we don't end up building kernels that will crash - Fix ARMv7M nommu initialisation (missing register initialisation) - Fix EFI decompressor entry (ensuring barrier instructions are enabled prior to use)" * tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: ARM: 8857/1: efi: enable CP15 DMB instructions before cleaning the cache ARM: 8856/1: NOMMU: Fix CCR register faulty initialization when MPU is disabled ARM: fix function graph tracer and unwinder dependencies
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git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linuxLinus Torvalds authored
Pull powerpc fixes from Michael Ellerman: "A one-liner to make our Radix MMU support depend on HUGETLB_PAGE. We use some of the hugetlb inlines (eg. pud_huge()) when operating on the linear mapping and if they're compiled into empty wrappers we can corrupt memory. Then two fixes to our VFIO IOMMU code. The first is not a regression but fixes the locking to avoid a user-triggerable deadlock. The second does fix a regression since rc1, and depends on the first fix. It makes it possible to run guests with large amounts of memory again (~256GB). Thanks to Alexey Kardashevskiy" * tag 'powerpc-5.1-6' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc/mm_iommu: Allow pinning large regions powerpc/mm_iommu: Fix potential deadlock powerpc/mm/radix: Make Radix require HUGETLB_PAGE
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git://git.kernel.dk/linux-blockLinus Torvalds authored
Pull block fixes from Jens Axboe: "A set of io_uring fixes that should go into this release. In particular, this contains: - The mutex lock vs ctx ref count fix (me) - Removal of a dead variable (me) - Two race fixes (Stefan) - Ring head/tail condition fix for poll full SQ detection (Stefan)" * tag 'for-linus-20190428' of git://git.kernel.dk/linux-block: io_uring: remove 'state' argument from io_{read,write} path io_uring: fix poll full SQ detection io_uring: fix race condition when sq threads goes sleeping io_uring: fix race condition reading SQ entries io_uring: fail io_uring_register(2) on a dying io_uring instance
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