- 27 Feb, 2012 1 commit
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Stephen Warren authored
This fixes the following compile error: CC arch/arm/boot/compressed/misc.o In file included from arch/arm/boot/compressed/misc.c:28:0: arch/arm/mach-tegra/include/mach/uncompress.h: In function 'arch_decomp_setup': arch/arm/mach-tegra/include/mach/uncompress.h:125:2: error: implicit declaration of function 'BUILD_BUG_ON_ZERO' [-Werror=implicit-function-declaration] cc1: some warnings being treated as errors This is due to use of the ARRAY_SIZE() macro. Typically, this would be solved by including <linux/bug.h>, but the compressor code isn't part of the kernel, and so should not include kernel headers. Instead, define the few macros the code uses directly, and in a way that doesn't depend on <linux/bug.h>. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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- 26 Feb, 2012 1 commit
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Stephen Warren authored
Commit 7da5a66 "irq_domain: Remove 'new' irq_domain in favour of the ppc one" changed the set of available irq domain APIs. Update the Tegra GPIO driver to account for those changes, to solve a build break. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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- 08 Feb, 2012 1 commit
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Stephen Warren authored
The new PMC driver now configures the PMU interrupt inversion, so board files don't need to poke the PMC registers directly to achieve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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- 07 Feb, 2012 31 commits
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Stephen Warren authored
This PMC driver is enough to parse the nvidia,invert-interrupt property from device tree, and configure the PMC's to honor that. In the future, this file could expand to centralize all other PMC accesses within the mach-tegra code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Laxman Dewangan authored
It is not require to move the requestor of dma to INVALID option before stopping dma. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Stephen Warren authored
Commit d91eeb0 "ARM: tegra: emc: device tree support" modified the EMC driver to create an EMC table from existing register settings when none was provided through platform data or device tree. This code wrote the wrong clock rate into the table; the actual rate in Hz, rather than the expected half-rate in KHz. This caused the BUG_ON in tegra2_emc_clk_round_rate() to fire, since that enormous rate could not be generated. Fixes: [ 2.425921] kernel BUG at arch/arm/mach-tegra/tegra2_clocks.c:1158! ... [ 2.618766] [<c001c0e8>] (tegra2_emc_clk_round_rate+0x58/0x70) from [<c00198b4>] (clk_round_rate+0x48/0x68) [ 2.628494] [<c00198b4>] (clk_round_rate+0x48/0x68) from [<c0019cc0>] (clk_set_rate_locked+0x40/0x68) [ 2.637707] [<c0019cc0>] (clk_set_rate_locked+0x40/0x68) from [<c0019d10>] (clk_set_rate+0x28/0x40) [ 2.646754] [<c0019d10>] (clk_set_rate+0x28/0x40) from [<c001ffc8>] (tegra_update_cpu_speed+0x54/0x144) [ 2.656144] [<c001ffc8>] (tegra_update_cpu_speed+0x54/0x144) from [<c002016c>] (tegra_target+0xb4/0xe0) [ 2.665538] [<c002016c>] (tegra_target+0xb4/0xe0) from [<c01a96c0>] (__cpufreq_driver_target+0x88/0xa4) [ 2.674931] [<c01a96c0>] (__cpufreq_driver_target+0x88/0xa4) from [<c01ac9d0>] (dbs_check_cpu+0x324/0x340) [ 2.684582] [<c01ac9d0>] (dbs_check_cpu+0x324/0x340) from [<c01aca40>] (do_dbs_timer+0x54/0xf4) [ 2.693277] [<c01aca40>] (do_dbs_timer+0x54/0xf4) from [<c00369a8>] (process_one_work+0x1d4/0x320) [ 2.702225] [<c00369a8>] (process_one_work+0x1d4/0x320) from [<c0036f34>] (worker_thread+0x134/0x230) [ 2.711437] [<c0036f34>] (worker_thread+0x134/0x230) from [<c003add0>] (kthread+0x80/0x8c) [ 2.719700] [<c003add0>] (kthread+0x80/0x8c) from [<c000ebf4>] (kernel_thread_exit+0x0/0x8) Reported-by: Marc Dietrich <marvin24@gmx.de> Signed-off-by: Stephen Warren <swarren@nvidia.com> [olof: fixed calculation of printed values] Signed-off-by: Olof Johansson <olof@lixom.net>
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Stephen Warren authored
Tegra20's GPIO controller has 7 banks, and Tegra30's controller has 8 banks. Allow the number of banks to be configured at run-time by the device tree. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Olof Johansson <olof@lixom.net>
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Stephen Warren authored
Enhance the driver to dynamically allocate the base IRQ number, and create an IRQ domain for itself. The use of an IRQ domain ensures that any device tree node interrupts properties are correctly parsed. Describe interrupt-related properties in the device tree binding docs, and the contents of "child" node interrupts property. Update tegra*.dtsi to specify the required interrupt-related properties. Finally, remove the definition of TEGRA_GPIO_TO_IRQ; this macro no longer gives correct results since the IRQ numbers for GPIOs are dynamically allocated. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Olof Johansson <olof@lixom.net>
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Stephen Warren authored
Replace compile-time usage of TEGRA_GPIO_TO_IRQ with run-time calls to gpio_to_irq(). This will allow the base IRQ number for the Tegra GPIO driver to be dynamically allocated in a later patch. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Olof Johansson <olof@lixom.net>
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Stephen Warren authored
uncompress.h now saves the selected UART's physical address in Tegra's IRAM, along with a cookie to indicate validity. The first time it's run, macro addruart in debug-macro.S looks for this cookie, and if it's present, uses the UART address stored there. If not, the static value TEGRA_DEBUG_UART_BASE is used, as was previous behaviour. The static behaviour will thus be used when not booting using a zImage. This work was inspired by work by Doug Anderson <dianders@chromium.org>; see http://lkml.org/lkml/2011/9/26/284. However, this patch relies on the data passing describe above, rather than duplicating the UART selection logic in debug-macro.S; the latest selection logic is more complex due to the need to check reset/clock bits too. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Doug Anderson <dianders@chromium.org> Acked-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Stephen Warren authored
With this change we automatically detect which UART to use for for printing during decompression. The detection involves coordination with the bootloader: it's expected that the bootloader will leave a 'D' (for [D]ebug) in the UART scratchpad register for whichever UART we should use for debugging. If we don't find any such UART, we fall back to the UART that was specified during config time: CONFIG_TEGRA_DEBUG_UART_XXX. As a side effect of this change, uncompress debug messages will work if you've specified CONFIG_TEGRA_DEBUG_UART_NONE, provided the bootloader obeys the protocol. This change is in line with what is documented in Documentation/arm/Booting. Other approaches considered: * Hardcode based on machine ID (as many other ARM boards do). OK, but nice to not have yet another place to add per-board code. Better to have bootloader parse device tree and pass us this info. * Check for TXE bit (like SA1110). Nice (and doesn't require a bootloader change), but a little less explicit. Also: if bootloader (for some reason) uses another UART, it needs to remember to turn it off before jumping to the kernel or we may print to it. NOTE: adapting this patch to check TXE too would be easy if desired. Signed-off-by: Doug Anderson <dianders@chromium.org> [swarren: Added clock/reset condition checks] Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Doug Anderson <dianders@chromium.org> Acked-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Doug Anderson authored
This will allow a future change to auto-detect which UART to use. Signed-off-by: Doug Anderson <dianders@chromium.org> [swarren: Extracted from a larger patch by Doug] Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Doug Anderson <dianders@chromium.org> Acked-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Doug Anderson authored
This removes the need for the variable "shift" in all functions in uncompress.h. Signed-off-by: Doug Anderson <dianders@chromium.org> [swarren: Extracted from a larger patch by Doug] Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Doug Anderson <dianders@chromium.org> Acked-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Stephen Warren authored
On Tegra20, the UART clock runs at 216MHz, whereas on Tegra30 it runs at 408MHz. Modify arch_decomp_setup() to detect Tegra20-vs-Tegra30 at run- time, and program the correct divisor. This makes uncompressor messages work correctly on Tegra30. This also fixes early printk, assuming zImage is used and this setup code runs. v2: Use CHIPID register to differentiate between chips, rather than a GIC register. This should be more future-proof. Volatile is required to prevent the compiler transforming the 32-bit apb_misc register read into an 8-bit read of address 1 higher, since the HW only supports 32- bit accesses, and will hang on an 8-bit access. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Laxman Dewangan authored
In order to read an accurate channel transfer count from the APB DMA engine, the DMA controller must be paused first. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Add device tree support to the emc driver, filling in the platform data based on the DT bindings. Changes since v1: * Unmangled some messed up patch squashes, moving changes to earlier patches * Flipped an of_property_read_u32 return value test * Clarified clock settings message on case where no table is provided Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Stephen Warren <swarren@nvidia.com>
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Olof Johansson authored
This is the first step in making it device-tree aware and get rid of the in-kernel EMC tables (of which there are none in mainline, thankfully). Changes since v3: * moved to devm_request_and_ioremap() in probe() Changes since v2: * D'oh -- missed a couple of variables that were added, never used and then later removed in a later patch. Changes since v1: * Fixed messed up indentation * Removed code that should be gone (was added here and removed later in series) Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Stephen Warren <swarren@nvidia.com>
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Olof Johansson authored
This is used by the memory setup code to pick the right memory timing table, if needed. Signed-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Add function to get chip revision, and print it out at boot time. Restructure the fuse access to just use cached variables instead of always reading the fuses, and export those variables directly instead of using accessor functions. Add a SKU ID table of currently known values. Based on code originally by Colin Cross <ccross@android.com>. Changes since v1: * Add A01 minor rev support * Don't decode for A03p on anything but T2x Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Stephen Warren <swarren@nvidia.com>
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Olof Johansson authored
Use the apbio dma functions for accessing the fuse registers. Signed-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Tegra2 hangs if APB registers are accessed from the cpu during an apb dma operation. The workaround is to use apb dma to read/write the registers instead. There is a dependency loop between fuses, clocks, and APBDMA. If dma is enabled, fuse reads must go through APBDMA to avoid corruption due to a hw bug. APBDMA requires a clock to be enabled. Clocks must read a fuse to determine allowable cpu frequencies. Separate out the fuse DMA initialization, and allow the fuse read and write functions to be called without using DMA before the DMA initialization has been completed. Access to the fuses before APBDMA is initialized won't hit the hardware bug because nothing else can be using DMA. Original fuse registar access code from Varun Wadekar <vwadekar@nvidia.com>, improved by Colin Cross <ccross@android.com> and later moved to separate driver by Jon Mayo <jmayo@nvidia.com>. Major refactoring/cleanup by Olof Johansson <olof@lixom.net>. Changes since v1: * fix 'return false' on error condition * dequeue dma ops in case of timeout From: Jon Mayo <jmayo@nvidia.com>. Signed-off-by: Jon Mayo <jmayo@nvidia.com>. Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Stephen Warren <swarren@nvidia.com>
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Olof Johansson authored
Since we'll do opportunistic allocations before the dma subsystem is enabled we want just silent failures and retries instead. Signed-off-by: Olof Johansson <olof@lixom.net>
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Leon Romanovsky authored
This patch is adding device tree support of headset autodetection on PAZ00 board. Signed-off-by: Leon Romanovsky <leon@leon.nu> Signed-off-by: Olof Johansson <olof@lixom.net>
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Leon Romanovsky authored
This patch adds initial device tree support of ALC5632 sound codec and machine driver for PAZ00 board. The implementation is based on the WM8903 codec. Signed-off-by: Marc Dietrich <marvin24@gmx.de> Signed-off-by: Leon Romanovsky <leon@leon.nu> Signed-off-by: Olof Johansson <olof@lixom.net>
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Stephen Warren authored
The Tegra PMC (Power Management Controller) interfaces with an external PMU (Power Management Unit), and controls wake-up from sleep modes. This initial binding is the bare minimum required to control the PMC's inversion of the PMU's interrupt signal. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Stephen Warren authored
Add complete bindings to instantiate and configure the codec and top-level audio complex on all currently supported boards using the Tegra+WM8903 audio driver. On those boards, disable the I2S2 controller since it isn't used. On boards not using the WM8903 codec, disable all the audio devices; they can be re-enabled once the relevant codec and ASoC machine drivers have been ported to device-tree. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Stephen Warren authored
This will allow the sound node to refer to the I2S controllers by name when creating phandles. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Stephen Warren authored
Adjust the dma-channel property name to match the binding implemented by the driver. The binding was implemented and documented in a separate change to the ASoC tree. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Stephen Warren authored
Document binding, and add the node to tegra*.dtsi. The driver isn't actually instantiated from this node yet, but the I2S binding will rely on being able to refer to the APB DMA node using a phandle. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Stephen Warren authored
The Tegra30 GPIO controller has one more bank than Tegra20, and hence has one more interrupt. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Olof Johansson <olof@lixom.net>
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Stephen Warren authored
The new content matches tegra20.dtsi, and is < 80 columns. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Olof Johansson <olof@lixom.net>
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Stephen Warren authored
Document the required reg and interrupts properties. Add a complete example. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Timings for the T25 version of seaboard, only one memory manufacturer and timing table (two speeds). Signed-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Device tree bindings for the EMC tables on tegra. Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Grant Likely <grant.likely@secretlab.ca>
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- 31 Jan, 2012 4 commits
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Linus Torvalds authored
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git://github.com/prasad-joshi/logfs_upstreamLinus Torvalds authored
There are few important bug fixes for LogFS * tag 'for-linus' of git://github.com/prasad-joshi/logfs_upstream: Logfs: Allow NULL block_isbad() methods logfs: Grow inode in delete path logfs: Free areas before calling generic_shutdown_super() logfs: remove useless BUG_ON MAINTAINERS: Add Prasad Joshi in LogFS maintiners logfs: Propagate page parameter to __logfs_write_inode logfs: set superblock shutdown flag after generic sb shutdown logfs: take write mutex lock during fsync and sync logfs: Prevent memory corruption logfs: update page reference count for pined pages Fix up conflict in fs/logfs/dev_mtd.c due to semantic change in what "mtd->block_isbad" means in commit f2933e86: "Logfs: Allow NULL block_isbad() methods" clashing with the abstraction changes in the commits 7086c19d: "mtd: introduce mtd_block_isbad interface" and d58b27ed: "logfs: do not use 'mtd->block_isbad' directly". This resolution takes the semantics from commit f2933e86, and just makes mtd_block_isbad() return zero (false) if the 'block_isbad' function is NULL. But that also means that now "mtd_can_have_bb()" always returns 0. Now, "mtd_block_markbad()" will obviously return an error if the low-level driver doesn't support bad blocks, so this is somewhat non-symmetric, but it actually makes sense if a NULL "block_isbad" function is considered to mean "I assume that all my blocks are always good".
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Linus Torvalds authored
Merge branch 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging * 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging: hwmon: (w83627ehf) Disable setting DC mode for pwm2, pwm3 on NCT6776F hwmon: (sht15) fix bad error code MAINTAINERS: Drop maintainer for MAX1668 hwmon driver MAINTAINERS: Add hwmon entries for Wolfson hwmon: (f71805f) Fix clamping of temperature limits
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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrlLinus Torvalds authored
Here are some fixes to the pin control system that has accumulated since -rc1. Mainly Tony Lindgren fixed the module load/unload logic and the rest are minor fixes and documentation. * 'for-torvalds' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: add checks for empty function names pinctrl: fix pinmux_hog_maps when ctrl_dev_name is not set pinctrl: fix some pinmux typos pinctrl: free debugfs entries when unloading a pinmux driver pinctrl: unbreak error messages Documentation/pinctrl: fix a few syntax errors in code examples pinctrl: fix pinconf_pins_show iteration
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- 30 Jan, 2012 2 commits
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git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/ttyLinus Torvalds authored
Here are some tty/serial patches for 3.3-rc1 Big thing here is the movement of the 8250 serial drivers to their own directory, now that the patch churn has calmed down. Other than that, only minor stuff (omap patches were reverted as they were found to be wrong), and another broken driver removed from the system. Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> * tag 'tty-3.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: serial: Kill off Moorestown code Revert "tty: serial: OMAP: ensure FIFO levels are set correctly in non-DMA mode" Revert "tty: serial: OMAP: transmit FIFO threshold interrupts don't wake the chip" serial: Fix wakeup init logic to speed up startup docbook: don't use serial_core.h in device-drivers book serial: amba-pl011: lock console writes against interrupts amba-pl011: do not disable RTS during shutdown tty: serial: OMAP: transmit FIFO threshold interrupts don't wake the chip tty: serial: OMAP: ensure FIFO levels are set correctly in non-DMA mode omap-serial: make serial_omap_restore_context depend on CONFIG_PM_RUNTIME omap-serial :Make the suspend/resume functions depend on CONFIG_PM_SLEEP. TTY: fix UV serial console regression jsm: Fixed EEH recovery error Updated TTY MAINTAINERS info serial: group all the 8250 related code together
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git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usbLinus Torvalds authored
Here are a bunch of USB patches for 3.3-rc1. Nothing major, largest thing here is the removal of some drivers that did not work at all. Other than that, the normal collection of bugfixes and new device ids. Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> * tag 'usb-3.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (52 commits) uwb & wusb: fix kconfig error USB: Realtek cr: fix autopm scheduling while atomic USB: ftdi_sio: Add more identifiers xHCI: Cleanup isoc transfer ring when TD length mismatch found usb: musb: omap2430: minor cleanups. qcaux: add more Pantech UML190 and UML290 ports Revert "drivers: usb: Fix dependency for USB_HWA_HCD" usb: mv-otg - Fix build if CONFIG_USB is not set USB: cdc-wdm: Avoid hanging on interface with no USB_CDC_DMM_TYPE usb: add support for STA2X11 host driver drivers: usb: Fix dependency for USB_HWA_HCD kernel-doc: fix new warning in usb.h USB: OHCI: fix new compiler warnings usb: serial: kobil_sct: fix compile warning: drivers/usb/host/ehci-fsl.c: add missing iounmap USB: cdc-wdm: better allocate a buffer that is at least as big as we tell the USB core USB: cdc-wdm: call wake_up_all to allow driver to shutdown on device removal USB: cdc-wdm: use two mutexes to allow simultaneous read and write USB: cdc-wdm: updating desc->length must be protected by spin_lock USB: usbsevseg: fix max length ...
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