- 25 Jan, 2019 25 commits
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Christian König authored
Otherwise we run into a non-retry fault on access. It seems to be a hardware bug that the executable bit has higher priority than the valid bit. v2: handle clears as well Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Move the BO on the LRU only when it is actually moved by a DMA operation. Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Tested-And-Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Evan Quan authored
User can use "pp_dpm_dcefclk" to retrieve and adjust dcefclock power levels. V2: expose this interface for Vega10 and later ASICs only Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
User can use "pp_dpm_fclk" to retrieve and adjust fclock power levels. V2: expose this interface for Vega20 and later ASICs only Signed-off-by:
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Evan Quan authored
User can use "pp_dpm_socclk" to retrieve and adjust SOC clock power levels. V2: expose this interface for Vega10 and later ASICs only Signed-off-by:
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Evan Quan authored
User can use "ppfeatures" sysfs interface to retrieve and set enabled powerplay features. V2: expose this feature for Vega10 and later dGPUs V3: squash in removal of unused variable (Alex) Signed-off-by:
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Chunming Zhou authored
if lru is changed, we cannot do bulk moving. v2: root bo isn't in bulk moving, skip its change. Signed-off-by:
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Chunming Zhou authored
allow driver do somethings when lru changed. v2: address Michel's comments. Signed-off-by:
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Aaron Liu authored
In some cases, psp response status is not 0 even there is no problem while the command is submitted. Some version of PSP FW doesn't write 0 to that field. So here we would like to only print a warning instead of an error during psp initialization to avoid breaking hw_init and it doesn't return -EINVAL. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Reviewed-by: Xiangliang Yu<Xiangliang.Yu@amd.com> Acked-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
Paul Menzel <pmenzel+amd-gfx@molgen.mpg.de> Signed-off-by:
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Oak Zeng authored
HW doorbell writing routing policy: writing to doorbell not in SDMA/IH/MM/ACV doorbell range will be routed to CP. So CP doorbell routing depends on doorbell range setting of above blocks. Setting doorbell range of above blocks earlier (soc15_common_hw_init) to make sure CP doorbell writing be routed to CP block. Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Reviewed-by:
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Oak Zeng authored
Different ASIC has different SDMA queue number so different SDMA doorbell range. Introduce an extra parameter to sdma_doorbell_range function and set sdma doorbell range correctly. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
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Oak Zeng authored
Different ASIC has different sdma doorbell range. Add a per device sdma_doorbell_range field and initialize it. Signed-off-by:
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Alex Deucher authored
Rather than just -1. Reviewed-by:
JimQu <Jim.Qu@amd.com> Signed-off-by:
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Rafał Miłecki authored
This fixes printing clock names in cases like: [ 5.352311] [drm] DM_PPLIB: values for Invalid clock [ 5.352313] [drm] DM_PPLIB: 400000 in kHz [ 5.352313] [drm] DM_PPLIB: 933000 in kHz [ 5.352314] [drm] DM_PPLIB: 1067000 in kHz [ 5.352315] [drm] DM_PPLIB: 1200000 in kHz [ 5.352317] [drm] DM_PPLIB: values for Invalid clock [ 5.352318] [drm] DM_PPLIB: 300000 in kHz [ 5.352318] [drm] DM_PPLIB: 600000 in kHz [ 5.352319] [drm] DM_PPLIB: 626000 in kHz [ 5.352320] [drm] DM_PPLIB: 654000 in kHz (source: HP EliteBook 745 G5 w. RAVEN 0x1002:0x15DD 0x103C:0x83D5 0xD1) On my system above "Invalid" names got replaced by "F" and "DCF". The same problem was occurring on Huawei Matebook D with just 667000 kHz instead of 400000 kHz. Signed-off-by:
Rafał Miłecki <rafal@milecki.pl> Signed-off-by:
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Matteo Croce authored
Fix spelling mistake: "lenght" -> "length" Signed-off-by:
Matteo Croce <mcroce@redhat.com> Signed-off-by:
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Jerry (Fangzhi) Zuo authored
Need to check if crtc state is changed so that mode set is required before trying to create new stream. It deals with the MST hotplug use case when plug back to the same connector where the failure to create new stream for the inactive crtc on the old connector. Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Jim Qu authored
Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Jim Qu authored
It will fall back to use mode1 reset if platform does not support BACO feature. v2: squash in warning fix (Alex) Signed-off-by:
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Jim Qu authored
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Jim Qu authored
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Jim Qu authored
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Jim Qu authored
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Jim Qu authored
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Jim Qu authored
V2: delay 20ms before BACO out. V3: rename function to vega10_baco_xxx Signed-off-by:
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Jim Qu authored
V2: squash in crash fix for non-register commands (Alex) Signed-off-by:
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- 14 Jan, 2019 15 commits
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Jim Qu authored
Signed-off-by:
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Jim Qu authored
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Leo Li authored
This is a follow up to: e28e1490794d ("drm/amd/display: Remove i2caux folder") Some files were still left, so delete all of them. CC: David Francis <David.Francis@amd.com> CC: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by:Leo Li <sunpeng.li@amd.com> Reviewed-by:
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Steven Chiu authored
Signed-off-by:
Steven Chiu <steven.chiu@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Krunoslav Kovac authored
[Wjy&How] Some stress test is causing unexpected memory allocation failure. This prevents null dereference but there will likely be problems later, hard to gracefully handle memalloc fail for critical objects. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Reza Amini <Reza.Amini@amd.com> Signed-off-by:
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Eric Bernstein authored
Check if VERT_FILTER_INIT_BOT and BLACK_OFFSET registers exists in the DCN SCL IP block before trying to access. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Bayan Zabihiyan authored
Modify freesync module to build VTEM infopackets when in HdmiVRR mode Signed-off-by:
Bayan Zabihiyan <Bayan.Zabihiyan@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Eric Yang authored
[Why] On DCN1, there is an issue where on high BW config on single channel systems, underflow will be observed if DCC is disabled. This issue can be observed on several use cases. For this particular case, it is observed when playing 4k video on 4k desktop with video downscaled to a certain size. [How] Block MPO for this particular case, this will prevent extra BW consumed from downscaling, working around the underflow. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Charlene Liu authored
[Why] DP compliance box shows wrong MSA data. Signed-off-by:
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Roman Li authored
[Why] Hotplug on raven results in REG_WAIT_TIMEOUT warning due to failing attempt to lock disabled otg for the hubp interdependent pipes programming. [How] Don't setup pipe interdependencies for disabled otg. Also removed the unnecessary duplicate logic checks. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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hersen wu authored
[WHY] clarify dal input parameters to pplib interface, remove un-used parameters. dal knows exactly which parameters needed and their effects at pplib and smu sides. current dal sequence for dcn1_update_clock to pplib: 1.smu10_display_clock_voltage_request for dcefclk 2.smu10_display_clock_voltage_request for fclk 3.phm_store_dal_configuration_data { set_min_deep_sleep_dcfclk set_active_display_count store_cc6_data --- this data never be referenced new sequence will be: 1. set_display_count --- need add new pplib interface 2. set_min_deep_sleep_dcfclk -- new pplib interface 3. set_hard_min_dcfclk_by_freq 4. set_hard_min_fclk_by_freq after this code refactor, smu10_display_clock_voltage_request, phm_store_dal_configuration_data will not be needed for rv. Signed-off-by:hersen wu <hersenxs.wu@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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David Francis authored
[Why] It is huge, unmaintainable, needlessly layered, and obsolete [How] Remove it. All of it. Also remove the i2caux struct in dc_context and the code that created and destructed it Signed-off-by:
David Francis <David.Francis@amd.com> Reviewed-by:
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David Francis authored
[Why] The aux_engine struct is needlessly complex and is defined multiple times. It contains function pointers that each have only one version and are called only from inside dce_aux. [How] Replace aux_engine with a new struct called dce_aux. Remove all function pointers and call functions directly. Remove unused functions Signed-off-by:
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David Francis authored
[Why] The old aux interface goes through i2caux and the aux_engine and engine function pointers. The multiple layers of indirection make it hard to tell waht is happening. The aux algorithm does not need to be this complicated: attempt to submit the request. If you get an ack (reply = 0), stop. Otherwise, retry, up to 7 times. [How] Add a new helper function in dce_aux that performs aux retries Move the plumbing of the aux calling code into dce_aux Add functions in ddc that redirect directly to dce_aux Make all aux calls use these functions Signed-off-by:
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