- 24 May, 2017 40 commits
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Hawking Zhang authored
programming pa_sc_raster_config/config1 reg is removed from gfx9 csb Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Hawking Zhang authored
Required for proper handshaking between the GFX and RLC. Signed-off-by:
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Hawking Zhang authored
Required for gfx powergating. Change-Id: I5a2f8f41253686d8bb776a92aa68bf90877ebaa8 Signed-off-by:
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Huang Rui authored
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Chunming Zhou authored
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Chunming Zhou authored
Fetch the correct ucode for raven. Signed-off-by:
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Chunming Zhou authored
Add the GFX9 golden settings. v2: squash in updates Signed-off-by:
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Chunming Zhou authored
Fetch correct firmware for raven for gfx and sdma. Signed-off-by:
Ken Wang <Qingqing.Wang@amd.com> Reviewed-by:
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Chunming Zhou authored
Set the appropriate ucode loading mechanism. Set to direct for now. Signed-off-by:
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Huang Rui authored
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Huang Rui authored
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Hawking Zhang authored
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Chunming Zhou authored
Add the common golden settings for Raven. Signed-off-by:
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Chunming Zhou authored
Add the IP blocks for RAVEN. v2: drop DC for upstream (Alex) Signed-off-by:
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Chunming Zhou authored
RAVEN is a new APU. Signed-off-by:
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Alex Deucher authored
Add registers for Video Controller Next 1.0 Signed-off-by: -
Alex Deucher authored
Add registers for THerMal control 10.0 Signed-off-by: -
Alex Deucher authored
Add registers for SDMA 4.1 Signed-off-by: -
Alex Deucher authored
Add registers for NBIO 7.0 Signed-off-by: -
Alex Deucher authored
Add registers for MP 10.0 Signed-off-by: -
Alex Deucher authored
Add registers for the MultiMedia Hub 9.1 Signed-off-by: -
Alex Deucher authored
Registers for Graphics Controller 9.1 Signed-off-by: -
Alex Deucher authored
Registers for Display Controller Next 1.0 Signed-off-by: -
Monk Liu authored
because if the fence is really signaled, it could already released so the fence pointer is a wild pointer, but if we use job->base.node we are safe because job will not be released untill amdgpu_job_timedout finished. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Signed-off-by:
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Monk Liu authored
1,TDR will kickout guilty job if it hang exceed the threshold of the given one from kernel paramter "job_hang_limit", that way a bad command stream will not infinitly cause GPU hang. by default this threshold is 1 so a job will be kicked out after it hang. 2,if a job timeout TDR routine will not reset all sched/ring, instead if will only reset on the givn one which is indicated by @job of amdgpu_sriov_gpu_reset, that way we don't need to reset and recover each sched/ring if we already know which job cause GPU hang. 3,unblock sriov_gpu_reset for AI family. V2: 1:put kickout guilty job after sched parked. 2:since parking scheduler prior to kickout already occupies a while, we can do last check on the in question job before doing hw_reset. TODO: 1:when a job is considered as guilty, we should mark some flag in its fence status flag, and let UMD side aware that this fence signaling is not due to job complete but job hang. 2:if gpu reset cause all video memory lost, we need introduce a new policy to implement TDR, like drop all jobs not yet signaled, and all IOCTL on this device will return ERROR DEVICE_LOST. this will be implemented later. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Monk Liu authored
We don't need a scheduler for KIQ. Signed-off-by:
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Monk Liu authored
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Monk Liu authored
that way we can know which job cause hang and can do per sched reset/recovery instead of all sched. Signed-off-by:
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Monk Liu authored
because we don't want to do sriov-gpu-reset under certain cases, so just split those two funtion and don't invoke sr-iov one from bare-metal one. V2: remove debugfs_gpu_reset routine on SRIOV case. Signed-off-by:
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Chunming Zhou authored
before that, we have function to check if reset happens by using reset count. v2: always update reset count after vm flush Signed-off-by:
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Chunming Zhou authored
v2: directly return for 'if' case. Signed-off-by:
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Chunming Zhou authored
this is an improvement for previous patch, the sched_sync is to store fence that could be skipped as scheduled, when job is executed, we didn't need pipeline_sync if all fences in sched_sync are signalled, otherwise insert pipeline_sync still. v2: handle error when adding fence to sync failed. Signed-off-by:
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Christian König authored
This kind of reset handling was removed a long time ago. v2: fix warning (Alex) Signed-off-by:
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Chunming Zhou authored
Signed-off-by:
Roger.He <Hongbo.He@amd.com> Reviewed-by:
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Chunming Zhou authored
the root cause is vram content is lost completely after pci reset. Signed-off-by:
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Roger.He authored
to cover below case: 1. A task gart bind/unbind but not add to adev->gtt_list yet 2. at this time gpu reset, gtt only recover those gtt in adev->gtt_list Reviewed-by:
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Alex Xie authored
Signed-off-by:
Alex Xie <AlexBin.Xie@amd.com> Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
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Alex Xie authored
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Alex Deucher authored
rather than defining it locally. Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
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Nikola Pajkovsky authored
else branch is pointless if it's right at the end of function and use unlikely() on err path. Reviewed-by:
Nikola Pajkovsky <npajkovsky@suse.cz> Signed-off-by:
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