- 27 Jun, 2017 14 commits
-
-
Sebastian Sanchez authored
Atomic bit tests are used to single errors and the completion of request submissions. These operations don't need to be atomic and show to be expensive on the profile. Replace each atomic bit operation with a bool type and a READ_ONCE/WRITE_ONCE pairing. Reviewed-by:
Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by:
Sebastian Sanchez <sebastian.sanchez@intel.com> Signed-off-by:
Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by:
Doug Ledford <dledford@redhat.com>
-
Sebastian Sanchez authored
The atomic SDMA_REQ_SEND_DONE bit is set by the process-level code, and then the same process-level code uses the bit to test that all packets have been submitted incurring a costly atomic read. Use a bool type with a READ_ONCE/WRITE_ONCE pairing for this bit, and use the same condition that is used to set the bit to test that all packets have been submitted. Reviewed-by:
-
Vishwanathapura, Niranjana authored
Provide the ability for IB clients to modify the OPA specific capability mask and include this mask in the subsequent trap data. Reviewed-by:
Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> Signed-off-by:
Michael N. Henry <michael.n.henry@intel.com> Signed-off-by:
-
Michael J. Ruhl authored
pci_enable_msix_range() and pci_disable_msix() have been deprecated. Updating to the new pci_alloc_irq_vectors() interface. Reviewed-by:
Michael J. Ruhl <michael.j.ruhl@intel.com> Signed-off-by:
-
Michael J. Ruhl authored
To improve the readability of function prototypes, give the parameters names in the affinity module. Reviewed-by:
-
Sebastian Sanchez authored
The current user SDMA request structure layout has holes. The cachelines can be reduced to improve cacheline trading. Separate fields in the following categories: mostly read, writable and shared with interrupt. Reviewed-by:
-
Sebastian Sanchez authored
An RB tree is used for the SDMA pinning cache. Cache entries are extracted and reinserted from the tree in case the address range for it changes. However, if the address range for the entry doesn't change, deleting the entry from the RB tree is not necessary. This affects performance since the tree needs to be rebalanced for each insertion, and this happens in the hot path. Optimize RB search by not removing entries when it's not needed. Reviewed-by:
Mitko Haralanov <mitko.haralanov@intel.com> Signed-off-by:
-
Mike Marciniszyn authored
SGEs that are contiguous needlessly consume driver dependent TX resources. The lkey validation logic is enhanced to compress the SGE that ends up in the send wqe when consecutive addresses are detected. The lkey validation API used to return 1 (success) or 0 (fail). The return value is now an -errno, 0 (compressed), or 1 (uncompressed). A additional argument is added to pass the last SQE for the compression. Loopback callers always pass a NULL to last_sge since the optimization is of little benefit in that situation. Reviewed-by:
Brian Welty <brian.welty@intel.com> Signed-off-by:
Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com> Signed-off-by:
-
Don Hiatt authored
We move many common IB fields into the hfi1_packet structure and set them up in a single function. This allows us to set the fields in a single place and not deal with them throughout the driver. Reviewed-by:
Dasaratharaman Chandramouli <dasaratharaman.chandramouli@intel.com> Reviewed-by:
Don Hiatt <don.hiatt@intel.com> Signed-off-by:
-
Don Hiatt authored
Calls to trace incoming packets will now receive the packet context as parameter. This enables trace support for future packet types. Header trace output is in the format <field>:<value> which makes parsing easier. input_ibhdr trace before change: <idle>-0 [001] d.h. 5904.250925: input_ibhdr: [0000:05:00.0] vl 0 lver 0 sl 0 lnh 2,LRH_BTH dlid 0002 len 18 slid 0001 op 0x64,UD_SEND_ONLY se 0 m 0 pad 0 tver 0 pkey 0xffff f 0 b 0 qpn 0x000001 a 0 psn 0x000001b2 deth qkey 0x80010000 sqpn 0x000001 input_ibhdr trace after change: <idle>-0 [001] d.h. 6655.714488: input_ibhdr: [0000:05:00.0] (IB) len:124 sc:0 dlid:0x0001 slid:0x0002 lnh:2,LRH_BTH lver:0 sl:0 age:0 becn:0 fecn:0 l4:0 rc:0 entropy:0 op:0x64,UD_SEND_ONLY se:0 m:0 pad:0 tver:0 pkey:0x7fff f:0 b:0 qpn:0x000001 a:0 psn:0x00000036 hlen:8 deth qkey:0x80010000 sqpn:0x000001 Reviewed-by:
-
Don Hiatt authored
Improve code readablity by adding inline functions to read specific BTH/IB fields without knowledge of byte offsets. Reviewed-by:
-
Ira Weiny authored
Leftover function that is not used. Remove it. Reviewed-by:
Ira Weiny <ira.weiny@intel.com> Signed-off-by:
-
Sebastian Sanchez authored
The tx request is unnecessarily initialized in the hot code path with memset(), however, there's no need to do this as most fields are initialized later on. this initialization shows to be costly in the profile. Remove unnecessary initialization from tx request and make sure all variables are initialized properly. Reviewed-by:
-
Doug Ledford authored
-
- 16 Jun, 2017 2 commits
-
-
Saeed Mahameed authored
Avoid touching RX QP RSS context when loading with only one RX ring, to allow optimized A0 RX steering. Enable by: - loading mlx4_core with module param: log_num_mgm_entry_size = -6. - then: ethtool -L <interface> rx 1 Performance tests: Tested on ConnectX3Pro, Intel(R) Xeon(R) CPU E5-2680 v3 @ 2.50GHz XDP_DROP packet rate: ------------------------------------- | Before | After | Gain | IPv4 | 20.5 Mpps | 28.1 Mpps | 37% | IPv6 | 18.4 Mpps | 28.1 Mpps | 53% | ------------------------------------- Signed-off-by:Saeed Mahameed <saeedm@mellanox.com> Signed-off-by:
Tariq Toukan <tariqt@mellanox.com> Cc: kernel-team@fb.com Cc: Eric Dumazet <edumazet@google.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
-
Tariq Toukan authored
Remove owner argument, as it is obsolete and unused. This also saves the overhead of calculating its value in data-path. Signed-off-by:
-
- 15 Jun, 2017 24 commits
-
-
Gustavo A. R. Silva authored
Value assigned to variable _data32_ at lines 1254 and 1257 is overwritten at line 1260 before it can be used. This makes such variable assignments useless. Addresses-Coverity-ID: 1227049 Signed-off-by:
Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by:
-
Vivien Didelot authored
The current code only assigns the default cpu_dp to all user ports of the switch to which the CPU port belongs. The user ports of the other switches of the fabric thus don't have a default CPU port. This patch fixes this by assigning the cpu_dp of all user ports of all switches of the fabric when the tree is fully parsed. Fixes: a29342e7 ("net: dsa: Associate slave network device with CPU port") Signed-off-by:
Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
-
David S. Miller authored
Hayes Wang says: ==================== r8152: support new chips These patches are used to support new chips. ==================== Signed-off-by: -
hayeswang authored
Add byte_enable for ocp_read_word() to replace reading 4 bytes data with reading the desired 2 bytes data. This is used to avoid the issue which is described in commit b4d99def ("r8152: remove sram_read"). The original method always reads 4 bytes data, and it may have problem when reading the PHY registers. The new method is supported since RTL8153B, but it doesn't influence the previous chips. The bits of the byte_enable for the previous chips are the reserved bits, and the hw would ignore them. Signed-off-by:
Hayes Wang <hayeswang@realtek.com> Signed-off-by:
-
hayeswang authored
This patch supports two new chips for RTL8153B. Signed-off-by:
-
hayeswang authored
The settings of the new chip are the same with RTL8152, except that its product ID is 0x8050. Signed-off-by:
-
David S. Miller authored
Thomas Falcon says: ==================== ibmvnic: LPM bug fixes This series of small patches is meant to resolve a number of bugs, mostly occurring during an ibmvnic driver reset when recovering from a logical partition migration (LPM). The first patch ensures that RX buffer pools are properly activated following an adapter reset by setting the proper flag in the pool data structure. The second patch uses netif_tx_disable to stop TX queues when closing the device during a reset. Third, fixup a typo that resulted in partial sanitization of TX/RX descriptor queues following a device reset. Fourth, remove an ambiguous conditional check that was resulting in a kernel panic as null RX/TX completion descriptors were being processed during napi polling while the device is closing. Finally, fix a condition where the napi polling routine exits before it has completed its work budget without notifying the upper network layers. This omission could result in the napi_disable function sleeping indefinitely under certain conditions. v2: Attempt to provide a proper cover letter ==================== Signed-off-by: -
Thomas Falcon authored
This patch fixes a bug where, in the case of a device reset, the polling routine will never complete, causing napi_disable to sleep indefinitely when attempting to close the device. Signed-off-by:
Thomas Falcon <tlfalcon@linux.vnet.ibm.com> Signed-off-by:
-
Thomas Falcon authored
Fix a kernel panic resulting from data access of a NULL pointer during device close. The pending_scrq routine is meant to determine whether there is a valid sub-CRQ message awaiting processing. When the device is closing, however, there is a possibility that NULL messages can be processed because pending_scrq will always return 1 even if there no valid message in the queue. It's not clear what this closing state check was originally meant to accomplish, so just remove it. Signed-off-by:
-
Thomas Falcon authored
Fixup a typo so that the entire SCRQ buffer is cleaned. Signed-off-by:
-
Thomas Falcon authored
Use netif_tx_disable to guarantee that TX queues are disabled when __ibmvnic_close is called by the device reset routine. Signed-off-by:
-
Thomas Falcon authored
RX buffer pools are disabled while awaiting a device reset if firmware indicates that the resource is closed. This patch fixes a bug where pools were not being subsequently enabled after the device reset, causing the device to become inoperable. Signed-off-by:
-
Shannon Nelson authored
As much as we'd like to play well with others, we really aren't handling the checksums on non-IP protocol packets very well. This is easily seen when trying to do TCP over ipv6 - the checksums are garbage. Here we restrict the checksum feature flag to just IP traffic so that we aren't given work we can't yet do. Orabug: 26175391, 26259755 Signed-off-by:
Shannon Nelson <shannon.nelson@oracle.com> Signed-off-by:
-
David S. Miller authored
Jiri Benc says: ==================== net: sched: act_tunnel_key: UDP checksums Currently, the tunnel_key tc action does not set TUNNEL_CSUM, thus transmitting packets with zero UDP checksum. This is inconsistent with how we treat non-lwt UDP tunnels where the default is to fill in the UDP checksum. Non-zero UDP checksum is the better default anyway for various reasons previously discussed. Make this configurable for the tunnel_key tc action with the default being non-zero checksum. Saves a lot of surprises especially with IPv6. Signed-off-by:
Jiri Benc <jbenc@redhat.com> ==================== Signed-off-by:
-
Jiri Benc authored
Allow requesting of zero UDP checksum for encapsulated packets. The name and meaning of the attribute is "NO_CSUM" in order to have the same meaning of the attribute missing and being 0. Signed-off-by:
-
Jiri Benc authored
There's currently no way to request (outer) UDP checksum with act_tunnel_key. This is problem especially for IPv6. Right now, tunnel_key action with IPv6 does not work without going through hassles: both sides have to have udp6zerocsumrx configured on the tunnel interface. This is obviously not a good solution universally. It makes more sense to compute the UDP checksum by default even for IPv4. Just set the default to request the checksum when using act_tunnel_key. Signed-off-by:
-
Gustavo A. R. Silva authored
Remove useless variable rxd_index and code related. Addresses-Coverity-ID: 1397691 Signed-off-by:
-
David S. Miller authored
Vivien Didelot says: ==================== net: dsa: prefix Global macros This patch series is the 2/3 step of the register definitions cleanup. It brings no functional changes. It prefixes and documents all Global (1) registers with MV88E6XXX_G1_ (or a specific model like MV88E6352_G1_STS_PPU_STATE), and prefers a 16-bit hexadecimal representation of the Marvell registers layout. The next and last patchset will prefix the Global 2 registers. ==================== Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
-
Vivien Didelot authored
Prefix and document the remaining Global IP and IEEE Priority and Core Tag Type registers and give them a clear 16-bit register representation. Signed-off-by:
-
Vivien Didelot authored
Prefix and document the Global Stats Operation and Counter registers and give them a clear 16-bit registers representation. Signed-off-by:
-
Vivien Didelot authored
Prefix and document the Global Monitor Control Register macros (which became the Global Monitor & MGMT Control Register with 88E6390) and give a clear 16-bit registers representation. Use __bf_shf to get the shift value at compile time instead of adding new defined macros for it. Signed-off-by:
-
Vivien Didelot authored
Prefix and document the Global Control and Control 2 registers macros and give a clear 16-bit registers representation. Signed-off-by:
-
Vivien Didelot authored
Prefix and document the Global VTU registers macros and give a clear 16-bit registers representation. Signed-off-by:
-
Vivien Didelot authored
Prefix and document the Global ATU Registers macros and give clear 16-bit registers representation. Signed-off-by:
-
