- 07 Jan, 2022 5 commits
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Mario Limonciello authored
This makes it clearer which codepaths are in use specifically in one state or the other. Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Acked-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Mario Limonciello authored
This codepath should be running in both s0ix and s3, but only does currently because s3 and s0ix are both set in the s0ix case. Signed-off-by:
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Evan Quan authored
To pair with the workaround which always reset the ASIC in suspend. Otherwise, the reset which relies on BACO will fail. Fixes: daf8de08 ("drm/amdgpu: always reset the asic in suspend (v2)") Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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James Yao authored
[why] Malicious mailbox event1 fails driver loading on vega10. A dummy event6 prevent driver from taking response from malicious event1 as its own. [how] On vega10, send a mailbox event6 before sending event1. Signed-off-by:
James Yao <yiqing.yao@amd.com> Reviewed-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Signed-off-by:
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yipechai authored
Enable sdma ecc interrupt event can be handled by event_interrupt_wq_v9. Signed-off-by:
yipechai <YiPeng.Chai@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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- 31 Dec, 2021 1 commit
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ssh://gitlab.freedesktop.org/agd5f/linuxDave Airlie authored
amd-drm-next-5.17-2021-12-30: amdgpu: - Suspend/resume fixes - Fence fix - Misc code cleanups - IP discovery fixes - SRIOV fixes - RAS fixes - GMC 8 VRAM detection fix - FRU fixes for Aldebaran - Display fixes amdkfd: - SVM fixes - IP discovery fixes Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211230141032.613596-1-alexander.deucher@amd.com
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- 30 Dec, 2021 34 commits
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Alex Deucher authored
Chips with no display hardware should return false for DC support. v2: drop Arcturus and Aldebaran Fixes: f7f12b25 ("drm/amdgpu: default to true in amdgpu_device_asic_has_dc_support") Reviewed-by:
Tareque Md.Hanif <tarequemd.hanif@yahoo.com> Signed-off-by:
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José Expósito authored
The "plane_state" pointer was access before checking if it was NULL. Avoid a possible NULL pointer dereference by accessing the plane address after the check. Addresses-Coverity-ID: 1493892 ("Dereference before null check") Fixes: 3f68c01b ("drm/amd/display: add cyan_skillfish display support") Signed-off-by:José Expósito <jose.exposito89@gmail.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Alex Deucher authored
If the platform suspend happens to fail and the power rail is not turned off, the GPU will be in an unknown state on resume, so reset the asic so that it will be in a known good state on resume even if the platform suspend failed. v2: handle s0ix Acked-by:
Luben Tuikov <luben.tuikov@amd.com> Acked-by:
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Evan Quan authored
By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some proper cleanups and put itself into a state ready for PNP. That can workaround some random resuming failure observed on BOCO capable platforms. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Yizhuo Zhai authored
In function enable_stream_features(), the variable "old_downspread.raw" could be uninitialized if core_link_read_dpcd() fails, however, it is used in the later if statement, and further, core_link_write_dpcd() may write random value, which is potentially unsafe. Fixes: 6016cd9d ("drm/amd/display: add helper for enabling mst stream features") Cc: stable@vger.kernel.org Signed-off-by:
Yizhuo Zhai <yzhai003@ucr.edu> Signed-off-by:
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Alex Deucher authored
It's not only supported by HG/PX laptops. It's supported by all dGPUs which supports BOCO/BACO functionality (runtime D3). BOCO - Bus Off, Chip Off. The entire chip is powered off. This is controlled by ACPI. BACO - Bus Active, Chip Off. The chip still shows up on the PCI bus, but the device itself is powered down. v2: fix missed HG/PX reference Reviewed-by: -
Marina Nikolic authored
== Description == Setting values of pm attributes through sysfs should not be allowed in SRIOV mode. These calls will not be processed by FW anyway, but error handling on sysfs level should be improved. == Changes == This patch prohibits performing of all set commands in SRIOV mode on sysfs level. It offers better error handling as calls that are not allowed will not be propagated further. == Test == Writing to any sysfs file in passthrough mode will succeed. Writing to any sysfs file in ONEVF mode will yield error: "calling process does not have sufficient permission to execute a command". Signed-off-by:
Marina Nikolic <Marina.Nikolic@amd.com> Acked-by:
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Tao Zhou authored
Otherwise the RAS error count couldn't be queried from sysfs. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Stanley.Yang <Stanley.Yang@amd.com> Signed-off-by:
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Guchun Chen authored
A minor typo. Signed-off-by:
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Wenjing Liu authored
[why] When reboot the link res map should be persisted. So during boot up, driver will look at the map to determine which link should take priority to use certain link res. This is to ensure that link res remains unshuffled after a reboot. Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] When there are more DP2.0 RXs connected than the number HPO DP link encoders we have, we need to dynamically allocate HPO DP link encoder to the port that needs it. [how] Only allocate HPO DP link encoder when it is needed. Tested-by:
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Wenjing Liu authored
[why] Update all accesses to use hpo dp link encoder through link resource only. Tested-by:
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Wenjing Liu authored
[why] This commit is to populate link res in preparation of the next commit. The next commit will replace all existing code to use link res instead Tested-by:
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Wenjing Liu authored
[why] There will be a series of re-arch changes in Link Resource Management. They are more and more muxable link resource objects and the resource is insufficient for a one to one allocation to all links created. Therefore a link resource sharing logic is required to determine which link should use certain link resource. This commit is the first one in this series that starts by defining a link resource struct, this struct will be available to all interfaces that need to perform link programming sequence. In later commits, we will granduately decouple link resource objects out of dc link. So instead of access a link resource from dc link. Current link's resource can be accessible through pipe_ctx->link_res during commit, or by calling dc_link_get_cur_link_res function with current link passed in after commit. Tested-by:
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Aric Cyr authored
This version brings along the following: - Fixes and improvements in the LTTPR code - Improve z-state - Fix null pointer check - Improve communication with s0i2 - Update multiple-display split policy - Add missing registers Tested-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Anthony Koo authored
Tested-by:
Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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Martin Leung authored
Undo ODM Combine regression causing causing pipe allocation issues. Tested-by:
Martin Leung <Martin.Leung@amd.com> Signed-off-by:
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Wesley Chalmers authored
[WHY] These registers are currently missing from the DCN303 header files Tested-by:
George Shen <George.Shen@amd.com> Acked-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Signed-off-by:
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Angus Wang authored
[WHY] Current implementation of pipe split policy prevents pipe split with multiple displays connected, which caused the MCLK speed to be stuck at max [HOW] Changed the pipe split policies so that pipe split is allowed for multi-display configurations Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1522 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1709 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1655 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403Tested-by:
Angus Wang <angus.wang@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] We'll exit optimized power state to do link detection but we won't enter back into the optimized power state. This could potentially block s2idle entry depending on the sequencing, but it also means we're losing some power during the transition period. [How] Hook up the handler like DCN21. It was also missed like the exit_optimized_pwr_state callback. Fixes: 64b1d0e8 ("drm/amd/display: Add DCN3.1 HWSEQ") Tested-by:
Eric Yang <Eric.Yang2@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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George Shen authored
[Why] DP spec specifies that DPRX shall use the read interval in the TRAINING_AUX_RD_INTERVAL_PHY_REPEATER LTTPR DPCD register. This register's bit definition is the same as the AUX read interval register for DPRX. [How} Remove logic which forces AUX read interval to 100us for repeaters when in LTTPR non-transparent mode. Tested-by:
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Nicholas Kazlauskas authored
[Why] Otherwise SMU won't mark Display as idle when trying to perform s2idle. [How] Mark the bit in the dcn31 codepath, doesn't apply to older ASIC. It needed to be split from phy refclk off to prevent entering s2idle when PSR was engaged but driver was not ready. Fixes: 118a3315 ("drm/amd/display: Add DCN3.1 clock manager support") Tested-by:
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Alvin Lee authored
[Why] Bug fix for null function ptr (should check for NULL instead of not NULL) [How] Fix if condition Tested-by:
Samson Tam <samson.tam@amd.com> Acked-by:
Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by:
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Lai, Derek authored
[Why] The change of setting a timer callback on boot for 10 seconds is still working, just lacked power down for DCN10. [How] Added power down for DCN10. Tested-by:
Derek Lai <Derek.Lai@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Stutter period won't be less than 5000.0, but if PSR is enabled then we can potentially enter Z9 when MPO is enabled. SMU will try to enter Z9 too early in these cases (before PSR is enabled) and we'll see underflow. [How] Block z-states (z9, z10) until we can add a new interface to SMU to signal when we can support z10 but not z9. We can revert this once the interface change is in. Tested-by:
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Shen, George authored
[Why] Current implementation is not scalable and retrofits the existing standard link training code for purposes outside of its original design. [How] Refactor vendor specific link training sequence into its own separate function to be called instead of the standard link training function. Tested-by:
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George Shen authored
[Why] Max link rate should be limited to the maximum link rate support by any LTTPR that are connected, including when operating in transparent mode. [How] Include transparent mode when factoring in LTTPR max supported link rate. Tested-by:
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Charlene Liu authored
[why] B0 PHY C map to F, D map to G driver use logic instance, dmub does the remap. Driver still need use the right PHY instance to access right HW. [how] use phyical instance when program PHY register. [note] could move resync_control programming to dmub next. Tested-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Signed-off-by:
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Surbhi Kakarya authored
If the event guard is enabled and VF doesn't receive an ack from PF for full access, the guest driver load crashes. This is caused due to the call to ttm_device_clear_dma_mappings with non-initialized mman during driver tear down. This patch adds the necessary condition to check if the mman initialization passed or not and takes the path based on the condition output. Signed-off-by:
Surbhi Kakarya <Surbhi.Kakarya@amd.com> Acked-by:
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Guchun Chen authored
This patch keeps the setting of sdma queue number to the same after recent KFD code refactor. Additionally, improve code to use switch case to list IP version to complete kfd device_info structure filling for IH version assignment. This makes consistency with the IP parse code in amdgpu_discovery.c. v2: use dev_warn for the default switch case; set default sdma queue per engine(8) and IH handler to v9. (Jonathan) v3: Fix missed IP version check of Raven. Fixes: f0dc99a6 ("drm/amdkfd: add kfd_device_info_init function") Signed-off-by:Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
Graham Sider <Graham.Sider@amd.com> Signed-off-by:
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Kent Russell authored
This is supported, although the offset is different from VG20, so fix that with a variable and enable getting the product name and serial number from the FRU. Do this for all SKUs since all SKUs have the FRU Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
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Kent Russell authored
On Aldebaran, the serial may be obtained from the FRU. Only overwrite the serial with the unique_id if the serial is empty. This will support printing serial numbers for mGPU devices where there are 2 unique_ids for the 2 GPUs, but only one serial number for the board Signed-off-by:
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Kent Russell authored
It's supported, so support the unique_id sysfs file Signed-off-by:
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Kent Russell authored
Having seen at least 1 42-character product_name, bump the number up to 64, and put that definition into amdgpu.h to make future adjustments simpler. Signed-off-by:
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