- 31 May, 2013 18 commits
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Daniel Vetter authored
This allows us to drop a bunch of ugly hacks and finally implement what commit cc464b2a Author: Paulo Zanoni <paulo.r.zanoni@intel.com> Date: Fri Jan 25 16:59:16 2013 -0200 drm/i915: set TRANSCODER_EDP even earlier tried to achieve, but that was reverted again in commit bba2181c Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Fri Mar 22 10:53:40 2013 +0100 Revert "drm/i915: set TRANSCODER_EDP even earlier" Now we should always have a consistent cpu_transcoder in the pipe_config. v2: Fix up the code as spotted by Paulo: - read the register for real - assign the right pipes - break out if the hw state doesn't make sense v3: Shut up gcc. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter authored
Well, as well as we can without completely revamping the drm vblank code. The issue are that - The vblank code needs to work on both ums and kms. - It deals always deals with pipes. - It doesn't take any of the kms locks. The last part is not really fixable without revamping the drm vblank code, since the drm core <-> driver interactions is a veritable pile of spaghettis. But the other pieces can be fixed by switching on the MODESET driver flag and either checking the hw state directly (ums case) or just querying our sw tracking (with broken locking, but that's not worse than what we've had). Note that this essentially reverts commit 702e7a56 Author: Paulo Zanoni <paulo.r.zanoni@intel.com> Date: Tue Oct 23 18:29:59 2012 -0200 drm/i915: convert PIPECONF to use transcoder instead of pipe for the ums case, which will fix a NULL deref (since we really don't have any crtcs set up). But the real reason to do this is to drop our reliance on the cpu_transcoder: By only checking intel_crtc->active we don't need to make sure that the pipe_config (or at least the cpu_transcoder) contain safe values even when the pipe is off. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by:
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Imre Deak authored
Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by:
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Imre Deak authored
The patch changes all remaining is_cpu_edp() check with a check for port A. We can do this, since in all these cases ValleyView is handled separately and port A is always a CPU side eDP port. Signed-off-by:
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Imre Deak authored
On ValleyView for both eDP and DP the AUX input clock is 200MHz, so we can calculate for both the clock divider for the 2MHz target rate at the same place. Afterwards we can also replace the is_cpu_edp() check with a check for port A. Signed-off-by:
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Imre Deak authored
Based on 3739850b - "drm/i915: disable the cpu edp port after the cpu pipe" and the bspec disabling sequence for IVB and older it seems we have to distinguish only the CPU vs. PCH port case, whether it's a DP or eDP doesn't seem to matter. For IVB and older on the CPU side we can only have eDP on port A, DP ports can only be on the PCH side. On VLV we have only CPU side eDP/DP ports, no PCH. So the condition for the disabling sequence we need for CPU ports is port == A || IS_VLV. This allows us to remove is_cpu_edp() completely in a later patch. v2: - simplify (and fix) the condition for CPU side ports and adjust the commit message accordingly (Daniel) Signed-off-by:
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Imre Deak authored
Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:
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Ben Widawsky authored
If contexts were actually initialized, and we fail somewhere later during init this would possibly leak memory, and lead to some error messages about unclean takedown. As the odds of this occurring, and someone actually caring/noticing are pretty slim, the patch isn't terribly important. Found by code inspection while working on something else. Signed-off-by:
Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
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Ben Widawsky authored
Add some debug messages to help figure out what goes wrong on context initialization. Later in the PPGTT series, I ended up having a lot of failures after reset. In many cases it was extra difficult to debug because I hadn't even realized that contexts failed to reinitialize after reset (again an artifact of some later patches). This fairly benign patch does help debug some potential issues which arise later. Signed-off-by:
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Ben Widawsky authored
I noticed this while doing the VMA abstraction. AFAICT, it won't actually fix anything, but it is the correct thing to do. Signed-off-by:
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Ben Widawsky authored
The GTT start is either 0 in the KMS case, or some value which is set only after the init IOCTL in the UMS case. In both cases, we don't have this information until after we've tried to kick out the firmware fb. This patch should have no functional change since we kzalloc the GTT struct anyway. It only clarifies the situation for people who end up having to look at that code. This weirdness was introduced in: commit 93d18799 Author: Ben Widawsky <ben@bwidawsk.net> Date: Thu Jan 17 12:45:17 2013 -0800 drm/i915: Remove use of gtt_mappable_entries Signed-off-by:
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Ben Widawsky authored
Since I'll need to modify i915_gem_object_bind_to_gtt(), fix the errors now to get checkpatch to not complain. Signed-off-by:
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Ben Widawsky authored
Found with kmemleak. Signed-off-by:
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Mika Kuoppala authored
In preparation to track per ring progress in hangcheck, add i915_hangcheck_ring_hung. v2: omit dev parameter (Ben Widawsky) Signed-off-by:
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Mika Kuoppala authored
Instead of relying in acthd, track ring seqno progression to detect if ring has hung. v2: put hangcheck stuff inside struct (Chris Wilson) v3: initialize hangcheck.seqno (Ben Widawsky) Signed-off-by:
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Mika Kuoppala authored
In preparation for next commit, pass seqno as a parameter to i915_hangcheck_ring_idle as it will be used inside i915_hangcheck_elapsed. Signed-off-by:
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Paulo Zanoni authored
On Haswell, whenever we change the sprites we need to completely recalculate all the watermarks, because the sprites are one of the parameters to the LP watermarks, so a change on the sprites may trigger a change on which LP levels are enabled. So on this commit we store all the parameters we need to store for proper recalculation of the Haswell WMs and then call haswell_update_wm. Notice that for now our haswell_update_wm function is not really using these parameters we're storing, but on the next commits we'll use these parameters. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Paulo Zanoni authored
Because we want to call it from the "sprite disable" paths, since on Haswell we need to update the sprite watermarks when we disable sprites. For now, all this patch does is to add the "enable" argument and call intel_update_sprite_watermarks from inside ivb_disable_plane. This shouldn't change how the code behaves because on sandybridge_update_sprite_wm we just ignore the "!enable" case. The patches that implement Haswell watermarks will make use of the changes introduced by this patch. Signed-off-by:
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- 23 May, 2013 12 commits
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Jani Nikula authored
We never check the return values, and there's not much we could do on errors anyway. Just simplify the signatures. No functional changes. Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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Jani Nikula authored
Rename all VLV IOSF sideband register accessor functions to vlv_<port>_{read,write}. No functional changes. Signed-off-by: -
Jani Nikula authored
The lower level sideband read/write functions already do this. Signed-off-by:
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Jani Nikula authored
Both the intel_dpio_{read,write} and valleyview_{punit,nc}_{read,write} use the IOSF sideband interface. They access the same registers and do mostly the same stuff, but no shared code. There are even duplicate register defines for the same registers. Both have locking, but the former use dpio_lock and the latter rps.hw_lock. It's racy. This patch refactors the sideband access to a single function that expects dpio_lock to be held. The dpio_lock is only used for sideband stuff, so it's a better match than rps.hw_lock for the purpose. The rps stuff still needs rps.hw_lock, since it's used to protect more than just the register access, so rps code will need to hold both locks. Based on the work by Shobhit Kumar <shobhit.kumar@intel.com> and Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>. Signed-off-by: -
Jani Nikula authored
Group both the HSW/LPT SBI interface and VLV IOSF sideband register accessor functions into a new file. No functional changes. v2: also move intel_sbi_{read,write} (Daniel) Signed-off-by: -
Mika Kuoppala authored
Sometimes when user is trying to get error state out from debugfs after gpu hang, the memory is low and/or fragmented enough that kmalloc in seq_file will fail. Prevent big kmalloc by avoiding seq_file and instead convert error state to string in smaller chunks. v2: better alloc flags, better truncate, correct locking, and error handling improvements (Chris Wilson) v3: printf annotations (Daniel Vetter) Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Ville Syrjälä authored
The 'struct' keyword was missing so struct drm_rect documentation never ended up in the generated docs. Also move the drm_rect documentations to a new section alognside the various helper functions and add a short description about the intended purpose of drm_rect. v2: Move to new section and add general description Signed-off-by:
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Thomas Meyer authored
Signed-off-by:
Thomas Meyer <thomas@m3y3r.de> Signed-off-by:
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Chris Wilson authored
In commit 25ff1195 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Thu Apr 4 21:31:03 2013 +0100 drm/i915: Workaround incoherence between fences and LLC across multiple CPUs we introduced an empirical workaround for memory corruption when using fences from multiple CPUs. At the time, we did not have any results for Valleyview, so the presumption was that it was limited to recent generations using LLC. Now we have evidence that Valleyview also suffers incoherence and requires a similar but different workaround. For Valleyview, the wbinvd instruction is insufficient and we require the serialising register write per-CPU. Conversely, that serialising register write is not enough for SNB/IVB/HSW. To compromise and keep the code relatively clean, employ both serialisation techniques in the same workaround. Reported-by:
Jon Bloomfield <jon.bloomfield@intel.com> Tested-by:
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Ville Syrjälä authored
WARN_ON(!spin_is_locked()) is not a good idea on a UP system w/o spinlock debugging. Use WARN_ON_SMP() instead. This check has been added in commit 8ba2d185 Author: Jani Nikula <jani.nikula@intel.com> Date: Fri Apr 12 15:18:37 2013 +0300 drm/i915: protect backlight registers and data with a spinlock Signed-off-by:
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Chris Wilson authored
This should help debugging the truly unexpected cases where it occurs - in particular to see which value is garbage. References: https://bugzilla.kernel.org/show_bug.cgi?id=58511Signed-off-by:
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Paulo Zanoni authored
Commit 1544d9d5 added a workaround inside haswell_init_clock_gating and mentioned it is "a workaround for early silicon revisions and should be removed later". This workaround is documented in bit 31 of PRI_CTL. I asked Arthur and he mentioned that setting FORCE_ARB_IDLE_PLANES replaces that workaround for the newer machines. So use the new one. Also notice that there's still another workaround for PRI_CTL that involves WM_DBG, but it's not the one we're reverting. And notice that we were previously setting WM_DBG_DISALLOW_MULTIPIPE_LP which disables the LP watermarks when more than one pipe is used, and we really don't want this because we need the LP watermarks if we want to reach deeper PC states. Signed-off-by:
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- 21 May, 2013 9 commits
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Paulo Zanoni authored
And the SNB_READ_WM0_LATENCY macro is not valid anymore because we have the "New WM0" at 63:56, so the "Old WM0" could maybe be zero if the new one is not zero. Signed-off-by:
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Paulo Zanoni authored
Remove the "placeholder" comment and set the actual value described by the specification. We still don't enable IPS, but it won't hurt to already have the value set here. While at it, fully set the register value instead of just masking the values we're changing. Signed-off-by:
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Paulo Zanoni authored
With this, that 338 can finally become the correct 337500. Due to the change we need to adjust the intel_dp_aux_ch function to set the correct value, so adjust the division and also use DIV_ROUND_CLOSEST instead of the old "round down" behavior because the spec says the value "should be programmed to get as close as possible to the ideal rate of 2MHz". Quoting Paulo's follow-up to a question from Chris Wilson to explain what exactly will change: I use the 337500 value on the next patch, when setting the ips_linetime value. The correct frequency is 337500, not 338000. ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, intel_ddi_get_cdclk_freq); For a mode with htotal of 2640 [0] we'll have: (i) (2640 * 1000 * 8) / 338000 = 62.48, resulting in 62 and (ii) (2640 * 1000 * 8) / 337500 = 62.57 resulting in 63. For the case inside intel_dp.c: Previously we were using 338. So with the old formula we were writing 338/2 = 169 to the register. And 337500 / 169 = 1997.04 (we use 337500 here because it's the real clock value). With the new value of 337500/2000 we'll have 168.75, which is 168 on the round-down case and 169 on the round-closest case. If we write 168 to the register, 337500 / 168 = 2008.92, and 2008.92 is more distant from 2000 than 1997.04. So with this patch we're changing the formula but still writing the same correct value to the DP AUX register. [0]: That's 1920x1080@50Hz on my DP monitor. Signed-off-by:
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Paulo Zanoni authored
Move the "*8" calculation to the left side so we don't propagate rounding errors. Also use DIV_ROUND_CLOSEST because that's what the spec says we need to do. Signed-off-by:
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Paulo Zanoni authored
... instead of mode->crtc_display. The spec says "pipe horizontal total number of pixels" and the "Haswell Watermark Calculator" tool uses the "Pipe H Total" instead of "Pipe H Src" as the value. Signed-off-by:
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Paulo Zanoni authored
The spec says the linetime watermarks must be programmed before enabling any display low power watermarks, but we're currently updating the linetime watermarks after we call intel_update_watermarks (and only at crtc_mode_set, not at crtc_{enable,disable}). So IMHO the best way guarantee the linetime watermarks will be updated before the low power watermarks is inside the update_wm function, because it's the function that enables low power watermarks. And since Haswell is the only platform that has linetime watermarks, let's completely kill the "intel_update_linetime_watermarks" abstraction and just use the intel_update_watermarks abstraction by creating haswell_update_wm. For now haswell_update_wm is still calling sandybridge_update_wm, but in the future I plan to implement a function specific to Haswell. v2: - Rename patch - Disable LP watermarks before changing linetime WMs (Chris) - Add a comment explaining that this is just temporary code. Signed-off-by: -
Paulo Zanoni authored
So don't call intel_update_linetime_watermarks from ironlake_crtc_mode_set. Only Haswell has these watermarks. Signed-off-by:
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Jesse Barnes authored
We can use this for fetching encoder specific pipe_config state, like mode flags, adjusted clock, etc. Just used for mode flags atm, so we can check the pipe config state at mode set time. v2: get_config when checking hw state too v3: fix DVO and LVDS mode flags (Ville) get SDVO DTD for flag fetch (Ville) v4: use input timings (Ville) correct command used (Ville) remove gen4 check (Ville) v5: get DDI flag config too Signed-off-by: -
Daniel Vetter authored
Backmerge Linux 3.10-rc2 since the various (rather trivial) conflicts grew a bit out of hand. intel_dp.c has the only real functional conflict since the logic changed while dev_priv->edp.bpp was moved around. Also squash in a whitespace fixup from Ben Widawsky for i915_gem_gtt.c, git seems to do something pretty strange in there (which I don't fully understand tbh). Conflicts: drivers/gpu/drm/i915/i915_reg.h drivers/gpu/drm/i915/intel_dp.c Signed-off-by:
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- 20 May, 2013 1 commit
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Linus Torvalds authored
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