1. 24 Feb, 2012 35 commits
    • Jesse Barnes's avatar
      Merge branch 'pci-next+probe_only+bus2res-fb127cb9' of... · ecd58d66
      Jesse Barnes authored
      Merge branch 'pci-next+probe_only+bus2res-fb127cb9' of git://github.com/bjorn-helgaas/linux into linux-next
      ecd58d66
    • Yinghai Lu's avatar
      PCI: add a PCI resource reallocation config option · b07f2ebc
      Yinghai Lu authored
      Add a new config option, PCI_REALLOC_ENABLE_AUTO, which will
      automatically try to re-allocate PCI resources if PCI_IOV support is
      enabled and the SR-IOV resources are unassigned.  Behavior can still be
      controlled using the pci=realloc= parameter.
      
      -v2: According to Jesse, adding one CONFIG option for distribution to
           disable it or enable it.
      -v3: update Kconfig text (jbarnes)
      Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      b07f2ebc
    • Yinghai Lu's avatar
      PCI: print out suggestion about using pci=realloc · eb572e7c
      Yinghai Lu authored
      let user know they could try if pci=realloc could help.
      
      -v2: update suggestion text.
      Suggested-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      eb572e7c
    • Yinghai Lu's avatar
      PCI: prepare pci=realloc for multiple options · b55438fd
      Yinghai Lu authored
      Let the user could enable and disable with pci=realloc=on or pci=realloc=off
      
      Also
      1. move variable and functions near the place they are used.
      2. change macro to function
      3. change related functions and variable to static and _init
      4. update parameter description accordingly.
      
      This will let us add a config option to control default behavior, and
      still allow the user to turn off automatic reallocation if it fails on
      their platform until a permanent solution is found.
      
      -v2: still honor pci=realloc, and treat it as pci=realloc=on
           also use enum instead of ...
      -v3: update kernel-paramenters.txt according to Jesse.
      Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
      Acked-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      b55438fd
    • Yinghai Lu's avatar
      PCI: Retry on IORESOURCE_IO type allocations · 0c5be0cb
      Yinghai Lu authored
      When enabling pci reallocation for a pci bridge, we clear the small size
      in in bridge and re-assign with requested + optional size for first
      several tries, but Ram mention could have problem with one case:
      	https://bugzilla.kernel.org/show_bug.cgi?id=15960
      
      After checking the booting log in
      	https://lkml.org/lkml/2010/4/19/44
      	[regression, bisected] Xonar DX invalid PCI I/O range since 977d17bb
      
      We should not stop too early for io ports.
      	Apr 19 10:19:38 [kernel] pci 0000:04:00.0: BAR 7: can't assign io (size 0x4000)
      	Apr 19 10:19:38 [kernel] pci 0000:05:01.0: BAR 8: assigned [mem 0x80400000-0x805fffff]
      	Apr 19 10:19:38 [kernel] pci 0000:05:01.0: BAR 7: can't assign io (size 0x2000)
      	Apr 19 10:19:38 [kernel] pci 0000:05:02.0: BAR 7: can't assign io (size 0x1000)
      	Apr 19 10:19:38 [kernel] pci 0000:05:03.0: BAR 7: can't assign io (size 0x1000)
      	Apr 19 10:19:38 [kernel] pci 0000:08:00.0: BAR 7: can't assign io (size 0x1000)
      	Apr 19 10:19:38 [kernel] pci 0000:09:04.0: BAR 0: can't assign io (size 0x100)
      and clear 00:1c.0 to retry again.
      
      This patch removes IORESOUCE_IO checking, and tries one more time.  It
      gives us a chance to get an allocation for the 00:1c.0 io port range
      because the range from 0x4000 to 0x8000 will be freed and we can use it.
      Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      0c5be0cb
    • Bjorn Helgaas's avatar
      PCI: collapse pcibios_resource_to_bus · fb127cb9
      Bjorn Helgaas authored
      Everybody uses the generic pcibios_resource_to_bus() supplied by the core
      now, so remove the ARCH_HAS_GENERIC_PCI_OFFSETS used during conversion.
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      fb127cb9
    • Bjorn Helgaas's avatar
      xtensa/PCI: get rid of device resource fixups · 4ba2aef3
      Bjorn Helgaas authored
      Tell the PCI core about host bridge address translation so it can take
      care of bus-to-resource conversion for us.
      
      CC: Chris Zankel <chris@zankel.net>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      4ba2aef3
    • Bjorn Helgaas's avatar
      sparc/PCI: get rid of device resource fixups · ac1edcc5
      Bjorn Helgaas authored
      Tell the PCI core about host bridge address translation so it can take
      care of bus-to-resource conversion for us.
      
      N.B. Leon apparently never uses initial BAR values, so it didn't matter
      that we never fixed up the I/O resources from bus address to CPU addresses.
      
      Other sparc uses pci_of_scan_bus(), which sets device resources directly
      to CPU addresses, not bus addresses, so it didn't need pcibios_fixup_bus()
      either.  But by telling the core about the offsets, we can nuke
      pcibios_resource_to_bus().
      
      CC: "David S. Miller" <davem@davemloft.net>
      CC: sparclinux@vger.kernel.org
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      ac1edcc5
    • Bjorn Helgaas's avatar
      sh/PCI: get rid of device resource fixups · 7fa6a50e
      Bjorn Helgaas authored
      Tell the PCI core about host bridge address translation so it can take
      care of bus-to-resource conversion for us.
      
      CC: Paul Mundt <lethal@linux-sh.org>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      7fa6a50e
    • Bjorn Helgaas's avatar
      powerpc/PCI: get rid of device resource fixups · 6c5705fe
      Bjorn Helgaas authored
      Tell the PCI core about host bridge address translation so it can take
      care of bus-to-resource conversion for us.
      
      CC: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      6c5705fe
    • Bjorn Helgaas's avatar
      parisc/PCI: get rid of device resource fixups · 39c2462e
      Bjorn Helgaas authored
      Tell the PCI core about host bridge address translation so it can take
      care of bus-to-resource conversion for us.
      
      CC: linux-parisc@vger.kernel.org
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      39c2462e
    • Bjorn Helgaas's avatar
      mn10300/PCI: get rid of device resource fixups · 4b84b6e9
      Bjorn Helgaas authored
      Tell the PCI core about host bridge address translation so it can take
      care of bus-to-resource conversion for us.
      
      CC: David Howells <dhowells@redhat.com>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      4b84b6e9
    • Bjorn Helgaas's avatar
      mips/PCI: get rid of device resource fixups · 96a6b9ad
      Bjorn Helgaas authored
      Tell the PCI core about host bridge address translation so it can take
      care of bus-to-resource conversion for us.
      
      Here's the wrinkle on Cobalt: we can't generate normal I/O port addresses
      on PCI because the GT-64111 doesn't do any address translation, so we have
      this:
      
        CPU I/O port addresses		[io 0x0000-0xffffff]
        PCI bus I/O port addresses	[io 0x10000000-0x10ffffff]
      
      Legacy-mode IDE controllers start out with the legacy bus addresses, e.g.,
      0x1f0, assigned by pci_setup_device().  These are outside the range of
      addresses GT-64111 can generate on PCI, but pcibios_fixup_device_resources()
      converted them to CPU addresses anyway by adding io_offset.  Therefore, we
      had to pre-adjust them in cobalt_legacy_ide_fixup().
      
      With io_offset = 0xf0000000, we had this:
      
        res->start = 0x1f0	initialized in pci_setup_device()
        res->start = 0x100001f0	-= io_offset in cobalt_legacy_ide_fixup()
        res->start = 0x1f0	+= io_offset in pcibios_fixup_device_resources()
      
      The difference after this patch is that the generic pci_bus_to_resource()
      only adds the offset if the bus address is inside a host bridge window.
      Since 0x1f0 is not a valid bus address and is not inside any windows, it is
      unaffected, so we now have this:
      
        region->start = 0x1f0	initialized in pci_setup_device()
        res->start = 0x1f0	no offset by pci_bus_to_resource()
      
      That means we can remove both pcibios_fixup_device_resources() and
      cobalt_legacy_ide_fixup().
      
      I would *rather* set the host bridge offset to zero (which corresponds
      to what the GT-64111 actually does), and have both CPU and PCI addresses
      of [io 0x10000000-0x10ffffff].  However, that would require changes to
      generic code that assumes legacy I/O addresses, such as pic1_io_resource
      ([io 0x0020-0x00021]), and we'd have to keep a Cobalt IDE fixup.
      
      Of course, none of this changes the fact that references to I/O port
      0x1f0 actually go to port 0x100001f0, not 0x1f0, on the Cobalt PCI bus.
      Fortunately the VT82C586 IDE controller only decodes the low 24 address
      bits, so it does work.
      
      CC: Ralf Baechle <ralf@linux-mips.org>
      CC: Yoichi Yuasa <yuasa@linux-mips.org>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      96a6b9ad
    • Bjorn Helgaas's avatar
      microblaze/PCI: get rid of device resource fixups · aa23bdc0
      Bjorn Helgaas authored
      Tell the PCI core about host bridge address translation so it can take
      care of bus-to-resource conversion for us.
      
      CC: Michal Simek <monstr@monstr.eu>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      aa23bdc0
    • Bjorn Helgaas's avatar
      ia64/PCI: get rid of device resource fixups · 10d1cd2b
      Bjorn Helgaas authored
      Tell the PCI core about host bridge address translation so it can take
      care of bus-to-resource conversion for us.
      
      CC: Tony Luck <tony.luck@intel.com>
      CC: Jack Steiner <steiner@sgi.com>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      10d1cd2b
    • Bjorn Helgaas's avatar
      ia64/PCI: SN: convert to pci_scan_root_bus() for correct root bus resources · f920b55d
      Bjorn Helgaas authored
      Convert from pci_scan_bus() to pci_scan_root_bus().  Supply the root
      bus resources from bussoft.  When we move the resource adjustment from
      pcibios_fixup_resources() to the PCI core, it will be important to have
      the root bus resources correct from the beginning.
      
      CC: Tony Luck <tony.luck@intel.com>
      CC: Jack Steiner <steiner@sgi.com>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      f920b55d
    • Bjorn Helgaas's avatar
      arm/PCI: get rid of device resource fixups · 9f786d03
      Bjorn Helgaas authored
      Tell the PCI core about host bridge address translation so it can take
      care of bus-to-resource conversion for us.
      
      CC: Russell King <linux@arm.linux.org.uk>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      9f786d03
    • Bjorn Helgaas's avatar
      alpha/PCI: get rid of device resource fixups · c04d9e35
      Bjorn Helgaas authored
      Tell the PCI core about host bridge address translation so it can take
      care of bus-to-resource conversion for us.
      
      CC: linux-alpha@vger.kernel.org
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      c04d9e35
    • Bjorn Helgaas's avatar
      PCI: add generic pcibios_resource_to_bus() · 36a66cd6
      Bjorn Helgaas authored
      This replaces the generic versions of pcibios_resource_to_bus() and
      pcibios_bus_to_resource() in asm-generic/pci.h with versions that use
      pci_resource_to_bus() and pci_bus_to_resource().
      
      The replacements are equivalent except that they can apply host
      bridge window offsets when the arch has supplied them by using
      pci_add_resource_offset().
      
      Each arch can convert to using pci_add_resource_offset() individually by
      removing its device resource fixups from pcibios_fixup_bus() and supplying
      ARCH_HAS_GENERIC_PCI_OFFSETS.  ARCH_HAS_GENERIC_PCI_OFFSETS can be removed
      after all have converted.
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      36a66cd6
    • Bjorn Helgaas's avatar
      PCI: convert bus addresses to resource when reading BARs · 5bfa14ed
      Bjorn Helgaas authored
      Some PCI host bridges translate CPU addresses to PCI bus addresses.
      Previously, we initialized pci_dev resources with PCI bus addresses,
      then converted them to CPU addresses later in arch-specific code
      (pcibios_fixup_resources()), which leaves a window of time where the
      pci_dev resources are incorrect.
      
      This patch adds support in the core for this address translation.
      When the arch creates the root bus, it can supply the host bridge
      address translation information, and the core can use it to set the
      pci_dev resources correctly from the beginning.
      
      This gives us a way to fix the problem that quirks that run between device
      discovery and pcibios_fixup_resources() fail because they use pci_dev
      resources that haven't been converted.  The reference below is to one
      such problem that affected ARM and ia64.
      
      Note that this patch has no effect until an arch starts using
      pci_add_resource_offset() with a non-zero offset: before that, all
      all host bridge windows have a zero offset and pci_bus_to_resource()
      copies the pci_bus_region directly to the struct resource.
      
      Reference: https://lkml.org/lkml/2009/10/12/405Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      5bfa14ed
    • Bjorn Helgaas's avatar
      PCI: add struct pci_host_bridge_window with CPU/bus address offset · 0efd5aab
      Bjorn Helgaas authored
      Some PCI host bridges apply an address offset, so bus addresses on PCI are
      different from CPU addresses.  This patch adds a way for architectures to
      tell the PCI core about this offset.  For example:
      
          LIST_HEAD(resources);
          pci_add_resource_offset(&resources, host->io_space, host->io_offset);
          pci_add_resource_offset(&resources, host->mem_space, host->mem_offset);
          pci_scan_root_bus(parent, bus, ops, sysdata, &resources);
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      0efd5aab
    • Bjorn Helgaas's avatar
      PCI: add struct pci_host_bridge and a list of all bridges found · 5a21d70d
      Bjorn Helgaas authored
      This adds a list of all PCI host bridges we find and a way to look up
      the host bridge from a pci_dev.
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      5a21d70d
    • Bjorn Helgaas's avatar
      PCI: don't publish new root bus until it's fully initialized · a5390aa6
      Bjorn Helgaas authored
      When pci_create_root_bus() adds the new struct pci_bus to the global
      pci_root_buses list, the bus becomes visible to other parts of the
      kernel, so it should be fully initialized.
      
      This patch delays adding the bus to the pci_root_buses list until after
      all the struct pci_bus initialization is finished.
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      a5390aa6
    • Bjorn Helgaas's avatar
      PCI: make pci_flags non-weak · 844393f4
      Bjorn Helgaas authored
      No architecture defines its own pci_flags, so the core symbol does not
      need to be weak.
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      844393f4
    • Bjorn Helgaas's avatar
      unicore32/PCI: use pci_flags PCI_PROBE_ONLY instead of arm-specific flag · b9c40b07
      Bjorn Helgaas authored
      CC: Guan Xuetao <gxt@mprc.pku.edu.cn>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      b9c40b07
    • Bjorn Helgaas's avatar
      powerpc/PCI: replace pci_probe_only with pci_flags · 673c9756
      Bjorn Helgaas authored
      We already use pci_flags, so this just sets pci_flags directly and removes
      the intermediate step of figuring out pci_probe_only, then using it to set
      pci_flags.
      
      The PCI core provides a pci_flags definition (currently __weak), so drop
      the powerpc definitions in favor of that.
      
      CC: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      CC: linuxppc-dev@lists.ozlabs.org
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      673c9756
    • Bjorn Helgaas's avatar
      powerpc/PCI: make pci_probe_only default to 0 · 3c13be01
      Bjorn Helgaas authored
      pci_probe_only is set on ppc64 to prevent resource re-allocation
      by the core. It's meant to be used in very specific circumstances
      such as when operating under a hypervisor that may prevent such
      re-allocation.
      
      Instead of default to 1, we make it default to 0 and explicitly
      set it in the few cases where we need it.
      
      This fixes FSL PCI which wants it clear among others.
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      3c13be01
    • Bjorn Helgaas's avatar
      mips/PCI: removed unused pci_probe configurability · 14be538c
      Bjorn Helgaas authored
      We never assign anything other than PCI_ASSIGN_ALL_BUSSES to pci_probe,
      so just remove the indirection.  If configurability is required in the
      future, please use the pci_flags/PCI_REASSIGN_ALL_BUS functionality
      as is done for powerpc.
      
      CC: Ralf Baechle <ralf@linux-mips.org>
      CC: linux-mips@linux-mips.org
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      14be538c
    • Bjorn Helgaas's avatar
      mips/PCI: replace pci_probe_only with pci_flags · 29090606
      Bjorn Helgaas authored
      Some architectures (alpha, mips, powerpc) have an arch-specific
      "pci_probe_only" flag.  Others use PCI_PROBE_ONLY in pci_flags for
      the same purpose.  This moves mips to the pci_flags approach so
      generic code can use the same test across all architectures.
      
      CC: Ralf Baechle <ralf@linux-mips.org>
      CC: linux-mips@linux-mips.org
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      29090606
    • Bjorn Helgaas's avatar
      microblaze/PCI: remove unused pci_flags · e5b36841
      Bjorn Helgaas authored
      pci_flags is initialized to zero and never modified (I think this was just
      copied from powerpc).  Therefore, "(pci_flags & XX)" is always false and
      "!(pci_flags & XX)" is always true, and we can remove all references
      to pci_flags.
      
      CC: Michal Simek <monstr@monstr.eu>
      CC: microblaze-uclinux@itee.uq.edu.au
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      e5b36841
    • Bjorn Helgaas's avatar
      arm/PCI: use pci_flags PCI_PROBE_ONLY instead of arm-specific flag · a4fab044
      Bjorn Helgaas authored
      CC: Russell King <linux@arm.linux.org.uk>
      CC: linux-arm-kernel@lists.infradead.org
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      a4fab044
    • Bjorn Helgaas's avatar
      arm/PCI: remove arch pci_flags definition · 6696cbc3
      Bjorn Helgaas authored
      The PCI core provides a pci_flags definition (currently __weak), so drop
      the arm definition in favor of that.
      
      We EXPORT_SYMBOL(pci_flags) as arm did previously.  I'm dubious about
      this: no other architecture exports it, and I didn't see any modules in
      the tree that reference it.
      
      CC: Rob Herring <rob.herring@calxeda.com>
      CC: Russell King <linux@arm.linux.org.uk>
      CC: linux-arm-kernel@lists.infradead.org
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      6696cbc3
    • Bjorn Helgaas's avatar
      alpha/PCI: replace pci_probe_only with pci_flags · 151d16d5
      Bjorn Helgaas authored
      Some architectures (alpha, mips, powerpc) have an arch-specific
      "pci_probe_only" flag.  Others use PCI_PROBE_ONLY in pci_flags for
      the same purpose.  This moves alpha to the pci_flags approach so
      generic code can use the same test across all architectures.
      
      CC: linux-alpha@vger.kernel.org
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      151d16d5
    • Bjorn Helgaas's avatar
      PCI: add pci_clear_flags() · dcce6dc4
      Bjorn Helgaas authored
      Add a pci_clear_flags() for cases when we statically initialize
      pci_flags, then decide to clear things out later.
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      dcce6dc4
    • Bjorn Helgaas's avatar
      PCI: make pci_flags always available · 47087700
      Bjorn Helgaas authored
      If we move resource assignment functions into the core, we'll still
      need a way for architectures to prevent reassignment, e.g., the
      "pci_probe_only" functionality, and we'll need a generic, always
      available way the core can test for that.  The "pci_flags"
      arrangement used by several architectures seems like a convenient
      way to do this.
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      47087700
  2. 23 Feb, 2012 5 commits
    • Alan Cox's avatar
      x86/mrst/pci: avoid SoC fixups on non-SoC platforms · 823806ff
      Alan Cox authored
      The PCI fixups get executed based upon whether they are linked in. We need
      to avoid executing them if we boot a dual SoC/PC type kernel on a PC class
      system.
      Signed-off-by: default avatarAlan Cox <alan@linux.intel.com>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      823806ff
    • Jacob Pan's avatar
      x86/mrst/pci: v4l/atomisp: treat atomisp as real pci device · 8ed30872
      Jacob Pan authored
      ATOMISP on Medfield is a real PCI device which should be handled differently
      than the fake PCI devices on south complex. PCI type 1 access is used for
      accessing config space this also has other impact such as PM D3 delay. There
      shouldn't be any need for reading base address from IUNIT via msg bus.
      Signed-off-by: default avatarJacob Pan <jacob.jun.pan@linux.intel.com>
      Signed-off-by: default avatarArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      8ed30872
    • Jacob Pan's avatar
      x86/mrst/pci: assign d3_delay to 0 for Langwell devices · 990a30c5
      Jacob Pan authored
      Langwell devices are not true pci devices, they are not subject to the 10 ms
      d3 to d0 delay required by pci spec. This patch assigns d3_delay to 0 for all
      langwell pci devices.
      
      We can also power off devices that are not really used by the OS
      Signed-off-by: default avatarJacob Pan <jacob.jun.pan@linux.intel.com>
      Signed-off-by: default avatarAlan Cox <alan@linux.intel.com>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      990a30c5
    • MUNEDA Takahiro's avatar
      PCI: Add pcie_hp=nomsi to disable MSI/MSI-X for pciehp driver · 7570a333
      MUNEDA Takahiro authored
      Add a parameter to avoid using MSI/MSI-X for PCIe native hotplug; it's
      known to be buggy on some platforms.
      
      In my environment, while shutting down, following stack trace is shown
      sometimes.
      
        irq 16: nobody cared (try booting with the "irqpoll" option)
        Pid: 1081, comm: reboot Not tainted 3.2.0 #1
        Call Trace:
         <IRQ>  [<ffffffff810cec1d>] __report_bad_irq+0x3d/0xe0
         [<ffffffff810cee1c>] note_interrupt+0x15c/0x210
         [<ffffffff810cc485>] handle_irq_event_percpu+0xb5/0x210
         [<ffffffff810cc621>] handle_irq_event+0x41/0x70
         [<ffffffff810cf675>] handle_fasteoi_irq+0x55/0xc0
         [<ffffffff81015356>] handle_irq+0x46/0xb0
         [<ffffffff814fbe9d>] do_IRQ+0x5d/0xe0
         [<ffffffff814f146e>] common_interrupt+0x6e/0x6e
         [<ffffffff8106b040>] ? __do_softirq+0x60/0x210
         [<ffffffff8108aeb1>] ? hrtimer_interrupt+0x151/0x240
         [<ffffffff814fb5ec>] call_softirq+0x1c/0x30
         [<ffffffff810152d5>] do_softirq+0x65/0xa0
         [<ffffffff8106ae9d>] irq_exit+0xbd/0xe0
         [<ffffffff814fbf8e>] smp_apic_timer_interrupt+0x6e/0x99
         [<ffffffff814f9e5e>] apic_timer_interrupt+0x6e/0x80
         <EOI>  [<ffffffff814f0fb1>] ? _raw_spin_unlock_irqrestore+0x11/0x20
         [<ffffffff812629fc>] pci_bus_write_config_word+0x6c/0x80
         [<ffffffff81266fc2>] pci_intx+0x52/0xa0
         [<ffffffff8127de3d>] pci_intx_for_msi+0x1d/0x30
        [<ffffffff8127e4fb>] pci_msi_shutdown+0x7b/0x110
         [<ffffffff81269d34>] pci_device_shutdown+0x34/0x50
         [<ffffffff81326c4f>] device_shutdown+0x2f/0x140
         [<ffffffff8107b981>] kernel_restart_prepare+0x31/0x40
         [<ffffffff8107b9e6>] kernel_restart+0x16/0x60
         [<ffffffff8107bbfd>] sys_reboot+0x1ad/0x220
         [<ffffffff814f4b90>] ? do_page_fault+0x1e0/0x460
         [<ffffffff811942d0>] ? __sync_filesystem+0x90/0x90
         [<ffffffff8105c9aa>] ? __cond_resched+0x2a/0x40
         [<ffffffff814ef090>] ? _cond_resched+0x30/0x40
         [<ffffffff81169e17>] ? iterate_supers+0xb7/0xd0
         [<ffffffff814f9382>] system_call_fastpath+0x16/0x1b
        handlers:
        [<ffffffff8138a0f0>] usb_hcd_irq
        [<ffffffff8138a0f0>] usb_hcd_irq
        [<ffffffff8138a0f0>] usb_hcd_irq
        Disabling IRQ #16
      
      An un-wanted interrupt is generated when PCI driver switches from
      MSI/MSI-X to INTx while shutting down the device.  The interrupt does
      not happen if MSI/MSI-X is not used on the device.
      I confirmed that this problem does not happen if pcie_hp=nomsi was
      specified and hotplug operation worked fine as usual.
      
      v2: Automatically disable MSI/MSI-X against following device:
          PCI bridge: Integrated Device Technology, Inc. Device 807f (rev 02)
      v3: Based on the review comment, combile the if statements.
      v4: Removed module parameter.
          Move some code to build pciehp as a module.
          Move device specific code to driver/pci/quirks.c.
      v5: Drop a device specific code until getting a vendor statement.
      Reviewed-by: default avatarKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
      Signed-off-by: default avatarMUNEDA Takahiro <muneda.takahiro@jp.fujitsu.com>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      7570a333
    • Yinghai Lu's avatar
      PCI: move pci_find_saved_cap out of linux/pci.h · 34a4876e
      Yinghai Lu authored
      Only one user in driver/pci/pci.c, so we don't need to put it in global
      pci.h
      Reviewed-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      34a4876e