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  1. 23 Jan, 2020 3 commits
  3. 16 Jan, 2020 2 commits
  5. 15 Jan, 2020 2 commits
  7. 13 Jan, 2020 1 commit
    • Linus Walleij's avatar
      pinctrl: dt-bindings: Fix some errors in the lgm and pinmux schema · 4784adc6
      Linus Walleij authored 
      This fixes some problems that caused build errors in the
lgm-io schema file:

- No "bindings" infix in the schema id
- Move the allOf inclusion for pinconf and pinmux nodes into
  the patternProperties for the -pins node
- We want "groups" not "group" to be compulsory for a pinmux
  node blended with a pin config node.
- Fix the generic pinmux-schema to list "groups" rather than
  "group" for a pinmux node, this might have led to some confusion.

This is a first user of the generic schema so a bit of a bumpy
road.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Rahul Tanwar <rahul.tanwar@linux.intel.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      4784adc6
  9. 09 Jan, 2020 4 commits
  11. 08 Jan, 2020 3 commits
  13. 07 Jan, 2020 13 commits
  15. 06 Jan, 2020 8 commits
  17. 31 Dec, 2019 4 commits
    • Geert Uytterhoeven's avatar
      sh: sh7269: Remove bogus SSU GPIO function definitions · b4fba344
      Geert Uytterhoeven authored 
      SH7269 has no Synchronous Serial Communication Unit (SSU).
Remove the bogus enum IDs, which caused holes in pinmux_func_gpios[].
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191218194812.12741-7-geert+renesas@glider.be
      b4fba344
    • Geert Uytterhoeven's avatar
      sh: sh7264: Remove bogus SSU GPIO function definitions · db9c0727
      Geert Uytterhoeven authored 
      SH7264 has no Synchronous Serial Communication Unit (SSU).
Remove the bogus enum IDs, which caused holes in pinmux_func_gpios[].
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191218194812.12741-6-geert+renesas@glider.be
      db9c0727
    • Geert Uytterhoeven's avatar
      pinctrl: sh-pfc: sh7269: Fix CAN function GPIOs · 02aeb2f2
      Geert Uytterhoeven authored 
      pinmux_func_gpios[] contains a hole due to the missing function GPIO
definition for the "CTX0&CTX1" signal, which is the logical "AND" of the
first two CAN outputs.

A closer look reveals other issues:
  - Some functionality is available on alternative pins, but the
    PINMUX_DATA() entries is using the wrong marks,
  - Several configurations are missing.

Fix this by:
  - Renaming CTX0CTX1CTX2_MARK, CRX0CRX1_PJ22_MARK, and
    CRX0CRX1CRX2_PJ20_MARK to CTX0_CTX1_CTX2_MARK, CRX0_CRX1_PJ22_MARK,
    resp. CRX0_CRX1_CRX2_PJ20_MARK for consistency with the
    corresponding enum IDs,
  - Adding all missing enum IDs and marks,
  - Use the right (*_PJ2x) variants for alternative pins,
  - Adding all missing configurations to pinmux_data[],
  - Adding all missing function GPIO definitions to pinmux_func_gpios[].

See SH7268 Group, SH7269 Group User’s Manual: Hardware, Rev. 2.00:
  [1] Table 1.4 List of Pins
  [2] Figure 23.29 Connection Example when Using Channels 0 and 1 as One
      Channel (64 Mailboxes × 1 Channel) and Channel 2 as One Channel
      (32 Mailboxes × 1 Channel),
  [3] Figure 23.30 Connection Example when Using Channels 0, 1, and 2 as
      One Channel (96 Mailboxes × 1 Channel),
  [4] Table 48.3 Multiplexed Pins (Port B),
  [5] Table 48.4 Multiplexed Pins (Port C),
  [6] Table 48.10 Multiplexed Pins (Port J),
  [7] Section 48.2.4 Port B Control Registers 0 to 5 (PBCR0 to PBCR5).
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191218194812.12741-5-geert+renesas@glider.be
      02aeb2f2
    • Geert Uytterhoeven's avatar
      pinctrl: sh-pfc: sh7264: Fix CAN function GPIOs · 55b1cb1f
      Geert Uytterhoeven authored 
      pinmux_func_gpios[] contains a hole due to the missing function GPIO
definition for the "CTX0&CTX1" signal, which is the logical "AND" of the
two CAN outputs.

Fix this by:
  - Renaming CRX0_CRX1_MARK to CTX0_CTX1_MARK, as PJ2MD[2:0]=010
    configures the combined "CTX0&CTX1" output signal,
  - Renaming CRX0X1_MARK to CRX0_CRX1_MARK, as PJ3MD[1:0]=10 configures
    the shared "CRX0/CRX1" input signal, which is fed to both CAN
    inputs,
  - Adding the missing function GPIO definition for "CTX0&CTX1" to
    pinmux_func_gpios[],
  - Moving all CAN enums next to each other.

See SH7262 Group, SH7264 Group User's Manual: Hardware, Rev. 4.00:
  [1] Figure 1.2 (3) (Pin Assignment for the SH7264 Group (1-Mbyte
      Version),
  [2] Figure 1.2 (4) Pin Assignment for the SH7264 Group (640-Kbyte
      Version,
  [3] Table 1.4 List of Pins,
  [4] Figure 20.29 Connection Example when Using This Module as 1-Channel
      Module (64 Mailboxes x 1 Channel),
  [5] Table 32.10 Multiplexed Pins (Port J),
  [6] Section 32.2.30 (3) Port J Control Register 0 (PJCR0).

Note that the last 2 disagree about PJ2MD[2:0], which is probably the
root cause of this bug.  But considering [4], "CTx0&CTx1" in [5] must
be correct, and "CRx0&CRx1" in [6] must be wrong.
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191218194812.12741-4-geert+renesas@glider.be
      55b1cb1f
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