- 14 Jan, 2020 28 commits
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John Clements authored
between UMC RAS err register access restore previous RSMU UMC index mode state Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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John Clements authored
in event of GPU reset, XGMI TA unload causes unrecoverable GPU hang Acked-by:
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Aaron Liu authored
Update mmSDMA0_UTCL1_WATERMK golden setting for renoir. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Aaron Liu authored
This patch updates SMU12_DRIVER_IF_VERSION to 11. Signed-off-by:
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Alex Deucher authored
We don't need to store the pre-OS console memory after the driver has loaded so free it. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
Leftover from bring up. We look up the actual pre-OS memory usage value later in the same function. Reviewed-by:
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Alex Deucher authored
It won't get used unless the driver allows the gtt domain for display buffers which is controlled elsewhere. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
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Alex Deucher authored
It should work on all Raven variants, but some users have reported issues with original Raven with IOMMU enabled. So far there have been no issues observed with PCO or RV2. v2: split out the dm init and domain changes into separate patches. Acked-by: -
Alex Deucher authored
It won't get used unless the driver allows the gtt domain for display buffers which is controlled elsewhere. Acked-by:
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Alex Deucher authored
All of the sdma stuff these were used for moves to the sdma code, so remove them. Reviewed-by:
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Tom St Denis authored
(v2): Fix preprocessor tag Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Hawking Zhang authored
sdma ras funcs are not supported by ASIC prior to vega20 Signed-off-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
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Guchun Chen authored
Hardcoded offset is not friendly. And another benifit of this patch is to keep read and write access to this register be consistent with other similar UMC regsiters in this file. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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Guchun Chen authored
Both are needed on vega20 and arcturus chip. Signed-off-by:
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Alex Deucher authored
Cast to make min() happy. The values are well within range. Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Kenneth Feng authored
change the sw ctf setting to smu_v11_0_set_thermal_range() since software_shutdown_temp shares the same definition and name in all the smu11 project. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Tiecheng Zhou authored
guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, as a consequence, the rev_id and external_rev_id are wrong. workaround it by hardcoding the rev_id to 0, which is the default value. v2. add comment in the code Signed-off-by:
Tiecheng Zhou <Tiecheng.Zhou@amd.com> Reviewed-by:
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Zhan Liu authored
[Why] There is a use case that link loss happens accidentally, and we need to recover that link loss as soon as possible. Under this circumstance, we will perform link training, and try to recover the link that's just lost. However, if link PHY is disabled before link training happens, then DP display will never come back again. Also, please note that dropping this disable_phy function call won't break USB-C hotplug functionality. (This line of code was firstly introduced associated with a patch to fix USB-C hotplug issue) [How] Don't disable DP transmitter and its encoder before link training happens, even if link loss is detected. Signed-off-by:
Zhan Liu <zhan.liu@amd.com> Reviewed-by:
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Hawking Zhang authored
SDMA edc counter registers were added in gfx edc counters array. When querying gfx error counter in that array, there is no way to differentiate sdma instance number for different asic and then results to NULL pointer access when trying to read sdma register base address for instances greater than 2 on Vega20. In addition, this also results to wrong gfx error counters since it actually added sdma edc counters. Therefore, sdma edc counter registers should be separated from gfx edc counter regsiter array and only get initialized when driver tries to enable sdma ras. Signed-off-by:
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Hawking Zhang authored
move ras_late_init and ras_fini to sdma_ras_funcs table Signed-off-by:
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Hawking Zhang authored
invoke sdma query_ras_error_count to get sdma single bit error count Signed-off-by:
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Hawking Zhang authored
query_ras_error_count function will be invoked to query single bit error count detected in sdma ip block Signed-off-by:
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Leo Liu authored
With default PSP FW loading Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Leo Liu authored
ucodes for instances are from different location Signed-off-by:
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Nirmoy Das authored
Do not ignore amdgpu_irq_add_id return value while registering VMC page fault interrupt. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Acked-by:
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Evan Quan authored
This can save users much troubles. As they do not actually need to care whether swSMU or traditional powerplay routine should be used. V2: apply the fixes to vi.c and cik.c also V3: squash in oops fix Signed-off-by:
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Yong Zhao authored
The SOC15_REG_OFFSET() macro needs to dereference adev->reg_offset[IP] pointer, which is sometimes NULL when there are fewer than 8 sdma engines. Avoid that by not initializing the array regardless. v2: squash in warning fixes Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Mikita Lipski authored
[why] Fix compilation warnings on i386 architecture: undefined reference to `__udivdi3' [how] Switch DIV_ROUND_UP to DIV64_U64_ROUND_UP Reported-by:
Randy Dunlap <rdunlap@infradead.org> Reviewed-by:
Mikita Lipski <mikita.lipski@amd.com> Signed-off-by:
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- 13 Jan, 2020 3 commits
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Dave Airlie authored
Merge tag 'amd-drm-next-5.6-2020-01-10-dp-mst-dsc' of git://people.freedesktop.org/~agd5f/linux into drm-next amd-drm-next-5.6-2020-01-10-dp-mst-dsc: drm: - Add MST helper for PBN calculation of DSC modes - Parse FEC caps on MST ports - Add MST DPCD R/W functions - Add MST helpers for virtual DPCD aux - Add MST HUB quirk - Add MST DSC enablement helpers amdgpu: - Enable MST DSC - Add fair share algo for DSC bandwidth calcs - Fix for 32 bit builds Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200110214328.308549-1-alexander.deucher@amd.com
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
amd-drm-next-5.6-2020-01-09: amdgpu: - Enable DCN support on POWER - Enable GFXOFF for Raven1 refresh - Clean up MM engine idle handlers - HDMI 2.0 audio fixes - Fixes for some 10 bpc EDP panels - Watermark fixes for renoir - SR-IOV fixes - Runtime pm robustness fixes - Arcturus VCN fixes - RAS fixes - BACO fixes for Arcturus - Stable pstate fixes for swSMU - HDCP fixes - PSP cleanup - HDMI fixes - Misc cleanups amdkfd: - Spread interrupt work across cores to reduce latency - Topology fixes for APUs - GPU reset improvements UAPI: - Enable DRIVER_SYNCOBJ_TIMELINE for vulkan - Return better error values for kfd process ioctl Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for v5.6: UAPI Changes: Cross-subsystem Changes: - Convert simple panel bindings to a template. Core Changes: - Revert drm-bridge-state changes, it causes a dependency error between drm and drm_kms_helper. - Fix when disabling crc's. - Assorted Kconfig fixes. Driver Changes: - Add ddc symlinks to more drivers. - Fix chained bridge handling in exynos and vc4. - More clock rate fixes in sun4i. - Add support for AUO B116XAK01, GiantPlus GPM940B0, Sony ACX424AKP, BOE NV140FHM-N49, Satoz SAT050AT40H12R2 and Sharp LS020B1DD01D panels. - Assorted small bugfixes. Signed-off-by:
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- 10 Jan, 2020 1 commit
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Mikita Lipski authored
[why] Compilation error "undefined reference to `__udivdi3'" was thrown on i386 architecture. [how] Use div_u64 for unsigned long division instead of a divide operator. Reported-by:
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- 09 Jan, 2020 8 commits
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Alex Deucher authored
the parameter is the mst manager, not the port. Reviewed-by:
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Alex Deucher authored
Otherwise we get undefined symbols. Reviewed-by:
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David (Dingchen) Zhang authored
[why] We need to minimally initialize the remote aux channel, e.g. the crc work struct of remote aux to dump the sink's DPRX CRCs in MST setup. [how] Add helper that only initializes the crc work struct of the remote aux, hooke crc work queue to 'drm_dp_aux_crc_work'. Then call this helper in DP MST port initialization. This, plus David Francis' patch [1], fix the issue of MST remote aux DPCD CRCs read. [1] https://patchwork.kernel.org/patch/11217941/ Cc: Leo Li <sunpeng.li@amd.com> Cc: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by:
David (Dingchen) Zhang <dingchen.zhang@amd.com> Reviewed-by:
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Mikita Lipski authored
Whenever a connector on an MST network is attached, detached, or undergoes a modeset, the DSC configs for each stream on that topology will be recalculated. This can change their required bandwidth, requiring a full reprogramming, as though a modeset was performed, even if that stream did not change timing. Therefore, whenever a crtc has drm_atomic_crtc_needs_modeset, for each crtc that shares a MST topology with that stream and supports DSC, add that crtc (and all affected connectors and planes) to the atomic state and set mode_changed on its state v2: Do this check only on Navi and before adding connectors and planes on modesetting crtcs v3: Call the drm_dp_mst_add_affected_dsc_crtcs() to update all affected CRTCs Reviewed-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
David Francis <David.Francis@amd.com> Signed-off-by:
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Mikita Lipski authored
[why] Whenever a connector on an MST network is changed or undergoes a modeset, the DSC configs for each stream on that topology will be recalculated. This can change their required bandwidth, requiring a full reprogramming, as though a modeset was performed, even if that stream did not change timing. [how] Adding helper to trigger modesets on MST DSC connectors by setting mode_changed flag on CRTCs in the same topology as affected connector v2: use drm_dp_mst_dsc_aux_for_port function to verify if the port is DSC capable v3: - added _must_check attribute - removed topology manager check - fix typos and indentations Reviewed-by: -
Mikita Lipski authored
[why] Since for DSC MST connector's PBN is claculated differently due to compression, we have to recalculate both PBN and VCPI slots for that connector. [how] The function iterates through all the active streams to find, which have DSC enabled, then recalculates PBN for it and calls drm_dp_helper_update_vcpi_slots_for_dsc to update connector's VCPI slots. v2: - use drm_dp_mst_atomic_enable_dsc per port to enable/disable DSC v3: - Iterate through connector states from the state passed - On each connector state get stream from dc_state, instead CRTC state Reviewed-by: -
Mikita Lipski authored
If driver fails to update update VCPI allocation during compute_mst_dsc_configs_for_state - fail the function by return early. Signed-off-by:
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David Francis authored
If there is limited link bandwidth on a MST network, it must be divided fairly between the streams on that network Implement an algorithm to determine the correct DSC config for each stream The algorithm: This [ ] ( ) represents the range of bandwidths possible for a given stream. The [] area represents the range of DSC configs, and the () represents no DSC. The bandwidth used increases from left to right. First, try disabling DSC on all streams [ ] (|) [ ] (|) Check this against the bandwidth limits of the link and each branch (including each endpoint). If it passes, the job is done Second, try maximum DSC compression on all streams that support DSC [| ] ( ) [| ] ( ) If this does not pass, then enabling this combination of streams is impossible Otherwise, divide the remaining bandwidth evenly amongst the streams [ | ] ( ) [ | ] ( ) If one or more of the streams reach minimum compression, evenly divide the reamining bandwidth amongst the remaining streams [ |] ( ) [ |] ( ) [ | ] ( ) [ | ] ( ) If all streams can reach minimum compression, disable compression greedily [ |] ( ) [ |] ( ) [ ] (|) Perform this algorithm on each full update, on each MST link with at least one DSC stream on it After the configs are computed, call dcn20_add_dsc_to_stream_resource on each stream with DSC enabled. It is only after all streams are created that we can know which of them will need DSC. Do all of this at the end of amdgpu atomic check. If it fails, fail check; This combination of timings cannot be supported. v2: Use drm_dp_mst_atomic_check to validate bw for certain dsc configurations v3: Use dc_dsc_policy structure to get min and max bpp rate for DSC configuration Acked-by:Wenjing Liu <Wenjing.Liu@amd.com> Signed-off-by:
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